Re: x86 AMX/ACE with >8 tiles

Christian Ludloff <[email protected]> Tue, 28 Jul 2026 13:11:59 -0700

Newsgroups	gmane.comp.gnu.binutils
Message-ID	<CAKSQd8Xsrxckabn6ZmtJ487sdATCD5x_abH=0ehu_dvZCO_0LQ@mail.gmail.com>

On Tue, Jul 28, 2026 at 12:49 AM Jan Beulich <[email protected]> wrote:
> On 27.07.2026 18:08, Christian Ludloff wrote:
> > The new COLSB and ROWS fields in TILECFG [...]
> Of course this re-sizing is wasteful for ACE's palette 2.

With AMX/ACE the CPUID-reported TILECFG operand width is
palette-independent.

> On that page you may actually want to note that the
> shown layout is only for palette 1.

Yes, for ACE the START_ROW and the COLSB and ROWS fields
are reserved MBZ -- page updated.

> Do the TILE_CTRL bits imply effects on XSTATE component
> size (and hence on CPUID output)?

Yes.

> I.e. can they be used to safely perform such migration?

Yes.

> Talking of TILE_CTRL, does setting bit 0 imply / require
> also setting bit 1?

Yes, for a 32-tile implementation. [0-31 or 0-15 or 0-7]
 No, for a 16-tile implementation. [bit1 = reserved MBZ]

> How is one to find out its MSR index?

The existing implementation supports querying as well as
relocating the index, i.e. it is flexible by design.

If Intel/AMD prefer a fixed index somewhere in their MSR
range, then they are of course free to allocate one.

> > Don't hard-code {LD,ST}TILECFG mem ops as 64-byte.
>
> This one is rather harder, as generally you want to be
> able to use compile-time-known operands / sizes.

Different tile count as well as different tile dimension
were a possibility from the get-go, back in ISE 040, and
they still are today, in SDM 092.

Personally, I actually like that.

From here on out, SW should no longer hard-code. And for
existing SW that did hard-code, 8-tile mode works.

> > Prepare for EVEX-encoded AMX, needed for 32 tiles.
>
> I assume the extension to ACE insns is pretty natural
> then, as everything that's needed can be encoded there.

Yes.

> Remains merely the question of whether a wider operand
> to LDTILECFG is really needed there.

You want the full CPUID-reported width because there may
be additional bits or fields beyond COLSB and ROWS.  :-)

> Perhaps for STTILECFG that's unavoidable, as you won't
> know what's to be stored.

Yes.

> Oh, also - are there intentions / desires to have this
> supported by gas and objdump?

A private patch exists.

It is straight-forward.

I'm not privy to plans.

Attached find a text file which describes the encodings.
If the mailing list strips it, then ping me directly.

--
C.

tile_16_32_opcodes.txt (text/plain, 4.1 KB)

; TMM16...31
;============

;--- corrections for {LD,ST}TILECFG memory operand width ------------------------------------------------------------------------------------------------------------

 VEX.128.NP.0F38.W0 49 !(11):000:bbb	LDTILECFG			M.TILECFG	; not Mz	; AMX_TILE|ACE
 VEX.128.66.0F38.W0 49 !(11):000:bbb	STTILECFG			M.TILECFG	; not Mz	; AMX_TILE|ACE

EVEX.128.NP.0F38.W0 49 !(11):000:bbb	LDTILECFG			M.TILECFG	; not Mz	; AMX_TILE|ACE			; APX|TMM16...31
EVEX.128.66.0F38.W0 49 !(11):000:bbb	STTILECFG			M.TILECFG	; not Mz	; AMX_TILE|ACE			; APX|TMM16...31

;--- previously added: not just APX, but also TMM16...31 ------------------------------------------------------------------------------------------------------------

EVEX.128.66.0F38.W0 4A !(11):rrr:100	TILELOADDRST1			rT,M.ib				; AMX_MOVRS			; APX|TMM16...31
EVEX.128.F2.0F38.W0 4A !(11):rrr:100	TILELOADDRS			rT,M.ib				; AMX_MOVRS			; APX|TMM16...31

EVEX.128.66.0F38.W0 4B !(11):rrr:100	TILELOADDT1			rT,M.ib				; AMX_TILE			; APX|TMM16...31
EVEX.128.F2.0F38.W0 4B !(11):rrr:100	TILELOADD			rT,M.ib				; AMX_TILE			; APX|TMM16...31

EVEX.128.F3.0F38.W0 4B !(11):rrr:100	TILESTORED			M.ib,rT				; AMX_TILE			; APX|TMM16...31

EVEX.128.NP.0F38.W0 6E !(11):rrr:100	T2RPNTLVWZ0			rT+1,M.ib			; AMX_TRANSPOSE			; APX|TMM16...31
EVEX.128.66.0F38.W0 6E !(11):rrr:100	T2RPNTLVWZ1			rT+1,M.ib			; AMX_TRANSPOSE			; APX|TMM16...31
EVEX.128.NP.0F38.W0 6F !(11):rrr:100	T2RPNTLVWZ0T1			rT+1,M.ib			; AMX_TRANSPOSE			; APX|TMM16...31
EVEX.128.66.0F38.W0 6F !(11):rrr:100	T2RPNTLVWZ1T1			rT+1,M.ib			; AMX_TRANSPOSE			; APX|TMM16...31

EVEX.128.NP.MAP5.W0 F8 !(11):rrr:100	T2RPNTLVWZ0RS			rT+1,M.ib			; AMX_TRANSPOSE,AMX_MOVRS	; APX|TMM16...31
EVEX.128.66.MAP5.W0 F8 !(11):rrr:100	T2RPNTLVWZ1RS			rT+1,M.ib			; AMX_TRANSPOSE,AMX_MOVRS	; APX|TMM16...31
EVEX.128.NP.MAP5.W0 F9 !(11):rrr:100	T2RPNTLVWZ0RST1			rT+1,M.ib			; AMX_TRANSPOSE,AMX_MOVRS	; APX|TMM16...31
EVEX.128.66.MAP5.W0 F9 !(11):rrr:100	T2RPNTLVWZ1RST1			rT+1,M.ib			; AMX_TRANSPOSE,AMX_MOVRS	; APX|TMM16...31

;--- newly added EVEX variants for TMM16...31 -----------------------------------------------------------------------------------------------------------------------

EVEX.128.NP.MAP5.W0 FD 11:rrr:bbb	TDPBF8PS			rT,mT,vT			; AMX_FP8
EVEX.128.66.MAP5.W0 FD 11:rrr:bbb	TDPHF8PS			rT,mT,vT			; AMX_FP8
EVEX.128.F3.MAP5.W0 FD 11:rrr:bbb	TDPHBF8PS			rT,mT,vT			; AMX_FP8
EVEX.128.F2.MAP5.W0 FD 11:rrr:bbb	TDPBHF8PS			rT,mT,vT			; AMX_FP8

EVEX.128.NP.0F38.W0 5D 11:rrr:bbb	TDPBUUD				rT,mT,vT			; AMX_INT8			; note: moved from opc=5E
EVEX.128.66.0F38.W0 5D 11:rrr:bbb	TDPBUSD				rT,mT,vT			; AMX_INT8			; note: moved from opc=5E
EVEX.128.F3.0F38.W0 5D 11:rrr:bbb	TDPBSUD				rT,mT,vT			; AMX_INT8			; note: moved from opc=5E
EVEX.128.F2.0F38.W0 5D 11:rrr:bbb	TDPBSSD				rT,mT,vT			; AMX_INT8			; note: moved from opc=5E

EVEX.128.F3.0F38.W0 5B 11:rrr:bbb	TDPBF16PS			rT,mT,vT			; AMX_BF16			; note: moved from opc=5C
EVEX.128.F2.0F38.W0 5B 11:rrr:bbb	TDPFP16PS			rT,mT,vT			; AMX_FP16			; note: moved from opc=5C

EVEX.128.NP.0F38.W0 6B 11:rrr:bbb	TCONJTCMMIMFP16PS		rT,mT,vT			; AMX_COMPLEX,AMX_TRANSPOSE
EVEX.128.66.0F38.W0 6B 11:rrr:bbb	TCONJTFP16			rT,mT				; AMX_COMPLEX,AMX_TRANSPOSE	; yes, 2-op
EVEX.128.F3.0F38.W0 6B 11:rrr:bbb	TTCMMRLFP16PS			rT,mT,vT			; AMX_COMPLEX,AMX_TRANSPOSE
EVEX.128.F2.0F38.W0 6B 11:rrr:bbb	TTCMMIMFP16PS			rT,mT,vT			; AMX_COMPLEX,AMX_TRANSPOSE

EVEX.128.NP.0F38.W0 6C 11:rrr:bbb	TCMMRLFP16PS			rT,mT,vT			; AMX_COMPLEX
EVEX.128.66.0F38.W0 6C 11:rrr:bbb	TCMMIMFP16PS			rT,mT,vT			; AMX_COMPLEX
EVEX.128.F3.0F38.W0 6C 11:rrr:bbb	TTDPBF16PS			rT,mT,vT			; AMX_BF16,AMX_TRANSPOSE
EVEX.128.F2.0F38.W0 6C 11:rrr:bbb	TTDPFP16PS			rT,mT,vT			; AMX_FP16,AMX_TRANSPOSE

EVEX.128.NP.0F38.W0 48 11:rrr:bbb	TTMMULTF32PS			rT,mT,vT			; AMX_TF32,AMX_TRANSPOSE
EVEX.128.66.0F38.W0 48 11:rrr:bbb	TMMULTF32PS			rT,mT,vT			; AMX_TF32

EVEX.128.F3.0F38.W0 5F 11:rrr:bbb	TTRANSPOSED			rT,mT				; AMX_TRANSPOSE			; yes, 2-op

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; EOF