testing

Hi Al.

there's something odd with the new tests from the 'testing' branch.

for example lang_verilog.1.gc, it outputs

[..]
#           v(V_cc)    v(in)      v(out)     iter(0)    vc(X1.q1)  vce(X1.q1)
 27.        20.        0.         0.         16.        10.213     9.2279    
#Freq       v(V_cc)    v(in)      v(amp_in)  v(out)    
 1.K        869.54p    0.2        0.099968   0.87954   
#           v(V_cc)    v(in)      v(out)     iter(0)   
 27.        20.        0.         0.         16.       
#Freq       v(V_cc)    v(in)      v(amp_in)  v(out)    
 1.K        796.25p    0.2        0.099968   0.80624 

this is produced by
print op v(V_cc) v(in) v(out) iter(0) vc(X1.q1) vce(X1.q1)
op
print ac v(V_cc) v(in) v(amp_in) v(out)
ac 1k
resistor #(100k) Rload (out 0);
op
ac

apparently, the "resistor" line eats the probes on X1.q1. is this a bug or a
feature?

cheers
felix