Re: fixes and subcircuits

Hi Al.

thanks for consideing the commits.

On Mon, Sep 07, 2015 at 12:56:45AM -0400, al davis wrote:
> > "subckt". make subcircuit implementation pluggable
> > (using dispatcher).
> 
> I don't understand the benefit of this one.
> e_subckt has the inheritable base class

the essential change is
-    MODEL_SUBCKT* new_module = new MODEL_SUBCKT;
+    CARD const* sckt = device_dispatcher["subckt"];
+    assert(sckt);
+    MODEL_SUBCKT* new_module = dynamic_cast<MODEL_SUBCKT*>(sckt->clone());
in lang_verilog.cc

i use this to inject a different MODEL_SUBCKT that carries a different
DEV_SUBCKT (via clone_instance). my deviant DEV_SUBCKT has a different
::expand implementation, one that is able to collapse nodes. this is
essential to (efficiently/accurately) simulate modules created by
lang_geda, such as

module some_resistor_schematic(p n);
net #() n1(p, p_int);
net #() n2(n, m_int);
place #(coords..) p1(p_int);
place #(coords..) p2(n_int);
RESISTOR #(..) (p_int,n_int);
endmodule.

you are right about e_subckt, the distance between SUBCKT_BASE and
DEV_SUBCKT is small enough, and i could just use the existing base.
however, i still need an inheritable MODEL_SUBCKT. do you agree? i will
prepare another patch..

cheers
felix