Re: events and step control

On Mon, Apr 15, 2019 at 03:57:27PM -0400, al davis wrote:
> On Mon, 15 Apr 2019 07:37:36 +0100
> Felix Salfelder <[email protected]> wrote:
> > in auto mode, a step is rejected and interferes with the inverter
> > transition. it seems the inverter forgets its state. is this a bug in
> > some logic tr_regress?
> 
> known bug .. see s_tr_swp.cc:516
>[..]
> The one you noticed, the one referenced above, has to do with behavior
> when a discrete event (control code 2) is rejected.  Apparently, the
> event happens prematurely, at the reschedule time.  It should be backed
> out and rescheduled, as would happen automatically with an analog event
> (control code 7).

i have had a quick look. a few edits to dev_logic.cc seem to improve it.
see evt-2 branch. it does affect the d_logic.01.* timing tests, and
needs a closer look, still.

> Logic device inputs, taking analog values, do not
> schedule cross events (code 7, see switch) so timing is sloppy.  Adding
> a switch to the netlist corrects this, but code should be in d_logic*.

will see where it fits in.

thanks!
felix