Re: possible nested modules bug

On Thu, 25 Feb 2021 02:13:29 +0100
Felix Salfelder <[email protected]> wrote:
> bug

There is a bug, but it's not what you might think.

The real bug is that nested modules are not supposed to work, as per
the Verilog standard.  The correct behavior would be to flag the nested
declaration as an error.

Then the search should only look in the root scope.

The search has other problems, most significantly that it is slow,
which is mostly caused by the linear search of everything.

Setting the owner before parsing might be a good thing to do in
general, but would probably make the search slower, which is a bigger
problem than the one you are asking about.

In this case, the official "fix" should be to disallow nested module
declarations, but keep in mind that some other language might be
different.

The whole way commands are interpreted in Verilog mode is strictly
incorrect, but that's another topic.