Re: sym to verilog-ams

On Sun,  3 Apr 2022 13:14:57 +0200 (CEST)
[email protected] wrote:
> The pintype attribute [1] does not line up with the verilog ones.
> According to [2], [3] is the only user of this and it checks which
> connections are allowed.


What you are calling "pintype" (in, out, io, and others) corresponds to
the port directions "input", "output" and "inout", but it is probably
best when converting a schematic to not specify this.  Rather, to
preserve the data, find a way to express in as an attribute (see
section 2.9 of VAMS-LRM-2-4.pdf).

Attributes as defined by section 2.9 are not yet supported by gnucap but
we can do a quick fix to treat them as comments, so you can use them,
but there is no need to.

In a schematic, we all use those symbols (pins with directions) to
express how we think of the pins, as inputs and outputs, but that is
usually incorrect in a simulation as a "conservative system", such as a
Spice-type simulation that Gnucap mostly does.

In Verilog, the easy and correct workaround is to just not use them.
Do not use the port declarations "input", "output" or "inout".

As an example, suppose my schematic is of an amplifier, with an input
and an output.  If you identify the pins as such, it may appear to
represent the intent, but in reality, both are "inout".  The pin we
think of as input is probably not ideal, but in reality has some
resistance, which makes it "inout".  Likewise, a real output is subject
to loading, so it too would be "inout".

To summarize, defining those terms ...

An "input" can sense the signal there, but has no effect on it.

An "output" can have an effect on the signal there, but cannot sense it
in any way.

An "inout" can do both.  It can sense what is there, and also have an
effect on it.

If the target is a Spice-type simulation, it's all "inout".
So-called Mixed-mode can have all 3.