Re: sym to verilog-ams

On Sun,  3 Apr 2022 13:14:57 +0200 (CEST)
[email protected] wrote:
> Can one have mult. identical modules or must a converter output
> just one ?


Officially, yes, but you need to provide some way to select which one
you want.  This is commonly done to implement things like "binning" and
the "level" parameter.

One way to select is `ifdef .  I won't discuss this one further because
it is familiar to everyone.

Another way is through a parameter, such as the "level" parameter that
Spice used to select different MOSFET models.

It would look something like this:

module nmos (d,g,s,b);
parameter level from [2:2];
.....
endmodule


module nmos (d,g,s,b);
parameter level from [12:13];
.....
endmodule


module nmos (d,g,s,b);
parameter level from [1:1];
.....
endmodule

The first one says that legal values for level are from 2 to 2,
inclusive.  ..fancy way to say that only the number 2 is allowed.


That's according to the standard.  Gnucap partially implements the
concept, with some hacks.

Another way, in the standard but not implemented in gnucap, is by
"attribute instance".

(* one *) module nmos (d,g,s,b);
....
endmodule

(* two *) .....

this example is probably wrong in details, but it expresses the idea.

Side note ...  Attribute instance is a way to stash metadata like
colors, fonts, where is the label, that could be used in rendering a
schematic.