implementing paramset for spice models

Hi there.

As we are making progress with Verilog language support, the issue with
Spice models stands out, as it is not covered by the standard. I believe
we need to improvise a bit to be able to access models written for Spice
from within a pure Verilog netlist, making full use of paramset.

The LRM only points out that models could be ported to Verilog-AMS (we
shall come to that...), and then paramset takes over the role of model
card. But this does not help, because we use unmodified models, as they
were written for spice3f5, ngspice, gnucap-modelgen and the like. I am
not aware of any software that builds this bridge, but I could imagine
it exists, somewhere in the dark. Has somebody seen it?

I started to describe the the situation in more detail at [1], and I
would like to conclude with useful conventions and a practical
implementation. Feel free to add to the list or comment.

Best wishes
felix

[1] http://gnucap.org/dokuwiki/doku.php/gnucap:paramset_spice