May'25 snapshots

Dear all,

Snapshots for Gnucap and Modelgen-Verilog [0,1] are available.

The most relevant change is the rework of the node data structures.
Both Gnucap and Modelgen-Verilog now support multiple ports bound to the
same node (IEEE1364 Section 12.3.3), as well as the ground declaration
from Verilog-AMS Section 3.6.4. A .global directive similar to NgSpice
manual Section 2.6, increases compatibility with the legacy.

These additions enable the effective use of many circuits compliant with
IEEE1364, without the need for lossy preprocessing such as "flattening".
It allows the analysis and simulation of schematics in their primary
format, such as [2].

For more detailed changes, see the corresponding entries in NEWS.

This project was funded through the NGI0 Entrust Fund, a fund
established by NLnet with financial support from the European
Commission's Next Generation Internet programme, under the aegis of DG
Communications Networks, Content and Technology under grant agreement No
101069594.

Best wishes
Felix

[0] https://git.savannah.gnu.org/cgit/gnucap.git/tag/?h=20250525-dev
[1] https://git.savannah.gnu.org/cgit/gnucap/gnucap-modelgen-verilog.git/tag/?h=20250525-dev
[2] http://gnucap.org/dokuwiki/doku.php/gnucap:user:netlist_import_and_export