Re: analog/code co-simulation and schematics and netlists for silicon

Peter Clifton wrote:
> On Wed, 2010-02-24 at 09:46 +1100, Geoff Swan wrote:
>> I have daydreamed about the possibility of linking gEDA with qucs and
>> simavr/gdb for example. 

My phone conversation today with Mr Wender of Triad was about verilog-ams and the
possibilities it offers mostly.  One way to get a model of a microprocessor
running with gnucap doing analog and gates might be to use CMOS logic gate primitives
that compute quickly and the usual models for analog elements and just let
it all run on a server farm for a few hours.  I'm not sure of the speed
gnucap will simulate flip flops and nand gates at when you put enough
together to make a working micro -- that's a lot of gates to sim.

I'll try to spend some more time on testing the gnetlist verilog-ams
back end with gnucap further, but first comes business survival.
It could be months.  Triad doesn't have a dedicate CAD guy to work
on this kind of integration.  Their sister company Viasic,
(Bill Cox and gnetman), does.  They're going to keep in touch about
gnetlist/gnucap integration -- no promises.

One thing to think about is what the NRE charges for a small
chip containing a 8051 micro and custom analog peripherals
would be with an open tool chain for simulation.  As things are
today Triad charges $200K NRE for a chip done by their staff
using Cadence licenses.  A DIY chip designed with gschem
and verilog-ams and simulated with gnucap would have  NRE charges
of only $30K per chip.  If a group of designs made with open tools
was ready at the same time they could syndicate a wafer run and get
the NRE charges down to $5K per batch per customer, (the shared slice
of the cost of a single metal mask).

al davis wrote:
The gnetlist backend only supports
 > a small subset of what could be done.
.
.
 > We really need a more general translator, that isn't based on
 > the gschem format or any other tool specific format.  I have a
 > start, but need help.
.
.
  What is lacking
 > is a fully working model compiler.  There is work in progress
 > with Icarus to make this happen.  The main missing piece now is
 > a back-end for Icarus that matches the gnucap interface.

Al, are you saying that Icarus verilog would run along side of
gnucap once that interface is ready?  Will Steve's model compiler
aim at doing user definable verilog-ams models?

Would you still use gschem/gnetlist to schematically connect
verilog modules?  That depends on having a good translator first, right?

Could you just use a top level schematic as a guide for connecting code
modules to simulate with no netlist generated from gschem?

John


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