Re: Problem with logic elements on transient simulation

Hi there.

On Mon, Nov 05, 2012 at 02:01:32PM -0500, al davis wrote:
> If you look inside the subckt, you will see that node 4 never 
> leaves the unknown state.  That's the bug.  The bug is that node 
> "0" doesn't work in logic mode.

this is really bad. now i remember having wasted lots on time on this
already... (but didn't fix it, *sigh*)

> As a workaround, instead of tying that digital node to 0 
> directly, tie it through a resistor.  Then the circuit works as 
> expected.

it's probably less time consuming to do one of these:
1) be verbose about it. for example issue a warning in DEV_LOGIC::map_nodes()
2) put _nstat[0].set_lv(lvSTABLE0); SIM_DATA::alloc_hold_vectors() for
   now (as its better in most cases).
3) add a node_t to MODEL_LOGIC (_m=_ttt=0, _lv="something that
   interprets gnd according to logic"), use it as "0" during
   DEV_LOGIC::map_nodes.

so, 1 would be helpful, 2 is a hack and 3 should be easy enough...

regards
felix