Re: prototype name -- bug or feature?

On Thursday 17 January 2013, Felix Salfelder wrote:
> to my surprise (in 0.36), this
> gnucap> verilog
> gnucap-verilog>capacitor #(.c(1)) resistor (.p(1),.n(2));
> gnucap-verilog>resistor r (1,2);
> gnucap-verilog>list
> 
> results in
> capacitor #(.c(1)) resistor (.p(1),.n(2));
> capacitor #(.c(1)) r (.p(1),.n(2));
> 
> a similar collision happened while parsing one of my geda
> schematics (also using LANGUAGE::find_proto), which is bad.
> i have no idea what to do, in case this is not a bug...

"find_looking_out" strikes again.

To decide what to do, let's ask a few more questions.

First, lets assume that the following is correct.  (is it?)

gnucap> verilog
gnucap-verilog>bogus r (1,2);
bogus r (1,2);
^ ? bogus: no match
gnucap-verilog>list
gnucap-verilog>

I believe this is correct because there is no type "bogus", and 
gnucap is correctly rejecting it.


Now, try this .....

gnucap> verilog
gnucap-verilog>capacitor #(.c(1)) bogus (.p(1),.n(2));
gnucap-verilog>bogus r (1,2);
gnucap-verilog>list
capacitor #(.c(1)) bogus (.p(1),.n(2));
capacitor #(.c(1)) r (.p(1),.n(2));
gnucap-verilog>

In this case, the capacitor's name is "bogus".  The next line 
declares another instance "r", which is a clone of bogus.

The question ....

Should the line beginning with "bogus" be rejected or not?

After answering that one, we can look at the original.

Does the Verilog spec say what is expected when there are 
duplicate labels?  missing labels?