Fwd: Re: [Qucs-devel] Status update / request for feedback / questions (AMS)

Forwarding this from the qucs list as it may be of interest.

Richard



-- 
The University of Edinburgh is a charitable body, registered in
Scotland, with registration number SC005336.


-------- Original Message --------
Subject: Re: [Qucs-devel] Status update / request for feedback / 
questions (AMS)
Date: Wed, 28 Aug 2013 00:36:04 -0700
From: Kevin Cameron <[email protected]>
To: Richard Crozier <[email protected]>
CC: [email protected]


Just FYI I did an integration of Icarus Verilog with GNUcap and another 
with Spice3 for mixed signal with Icarus being loaded as a shared library -

http://iverilog.wikia.com/wiki/GIT_Branch_Summary - embedded-vvp (the 
bulk of the code, C++)

For GNUcap/Spice I just modified the PWL sources to call out to the 
dynamically loaded code for data points, and for Icarus I added VPI code 
to locate the (non-blocking) assignments and convert them to PWL data. I 
added truncation code in the PWL sources to catch the logic thresholds 
on A->D boundary. Control gets handed to the subordinate simulators 
between solving and final acceptance (as far as I can remember).

Can probably get it working again if anyone is interested.

Kev.