wire type of net in verilog-ams

I see this in the verilog-ams_2.3 LRM from http://www.eda.org/verilog-ams/ and am not sure how to read it.


"3.6.2.4 Discipline of nets and undeclared nets
It is possible for a module to have nets where there are no discipline declarations. If such a net appears
bound only to ports in module instantiations, it may have no declaration at all or may be declared to have a
net type such as wire, tri, wand, wor, etc. If it is referenced in behavioral code, then it must have a net
type."
<snip>
"This allows netlists (modules that describe connectivity only, with no behavior) that use wire as an inter-
connect to be valid in both IEEE std 1364-2005 Verilog HDL and Verilog-AMS HDL. The domain shall be
determined by the connectivity of the net (see 7.4)."

Seems like they allow for wire, and get the electrical domain from what it touches, if I read it right.

This might match the way Mike Jarabek's gnetlist plugin is now -- it outputs
wire A;
for a net named A.


So, should schematic wires generating a netlist for gnucap be
wire a;
or
electrical A;
?

If I can use the     wire A;    form the same scheme code gnetlist plugin can handle both verilog 2001 and verilog-ams(gnucap)

John

-- 
Ecosensory   Austin TX