gnucap with verilog-ams netlist input

Hi,

How do I connect a gnucap internal capacitor model to this netlist generated by gnetlist -g verilog?

/* structural Verilog generated by gnetlist */
/* WARNING: This is a generated file, edits */
/*        made here will be lost next time  */
/*        you run gnetlist!                 */
/* Id ..........$Id$ */
/* Source.......$Source$ */
/* Revision.....$Revision$ */
/* Author.......$Author$ */

module verilog_io (    GND ,    C ,    A  );

/* Port directions begin here */
inout GND ;
inout C ;
inout A ;


/* Wires from the design */
//electrical B ;
//electrical GND ;
//electrical C ;
//electrical A ;

/* continuous assignments */

/* Package instantiations */
cap #(.value(1250e-9) ) C1 ( .p(B), .n(GND));

ind #(.l(.001) ) L1 ( .n(C), .p(B));

res #(.r(1000) ) R1 ( .n(B), .p(A));

endmodule


Thanks,

John Griessen

-- 
Ecosensory   Austin TX