Re: gnucap with verilog-ams netlist input

I fixed up the netlist, and seem to be getting models instantiated.

bare bones verilog-ams netlist w/o comments:
========================================
module verilog_io (    GND ,    C ,    A  );

capacitor #(.c(1250e-9) ) C1 ( .p(B), .n(GND));

inductor #(.l(.001) ) L1 ( .n(C), .p(B));

resistor #(.r(1000) ) R1 ( .n(B), .p(A));

endmodule
=========================

and here's output:

gnucap-verilog>list
module verilog_io (GND,C,A);
// Port directions begin here
// Wires from the design
// continuous assignments
// Package instantiations
capacitor #(.c( 1.25u)) C1 (.p(B),.n(GND));
inductor #(.l( 0.001)) L1 (.p(B),.n(C));
resistor #(.r( 1.K)) R1 (.p(A),.n(B));
endmodule // verilog_io


So now all I need is some input signal and I can run a simulation!

Thanks,

John Griessen

Ecosensory   Austin TX