Re: verilog-ams instance loading

al davis wrote:
> Try switching around the names:
> 
> verilog_io  verilog_io1  ( .GND(0) , OUT(VOUT), .IN(VIN));


gnucap-verilog>get ./verilog_io.net
// structural Verilog generated by gnetlist
verilog_io verilog_io1 ( .GND(0) , .OUT(VOUT), .IN(VIN));
^ ? v: no match

gnucap-verilog>get ./verilog_io.net
// structural Verilog generated by gnetlist
module verilog_io verilog_io1 ( .GND(0) , .OUT(VOUT), .IN(VI
                   ^ ? '(' required

Hmmm....  that wasn't a good use of volunteer time.... or yours...  no results.

Is there a way to instantiate and
simulate a verilog-ams module?

What would it be like to change the verilog-ams input parsing?  What kind of version control methods do you use
for dealing with volunteer code patches?  Will you point  me to the place to look in the code?

Is changing verilog-ams input parsing in the category of "usability coding"
that you have written about dropping in favor of "forward progress coding"?  I paraphrased -- not quoting you and may have read wrong.

John Griessen