Re: testing verilog netlist input

On Monday 09 February 2009, John Griessen wrote:
> So, next I'm going to try spice mode to enter a vsource.
> Is that the way to do it now?  If so, should I keep in spice
> mode and follow an example of spice simulation to do a run?

As you know, there is incomplete work there.

If you need something that is available in one language but not 
another, make a wrapper.

In this case ....   The sources with all the fancy stuff still 
use old code "obsolete_callback" that doesn't work in Verilog.  
For now, it only works in spice mode.  This will be fixed 
before the stable release, but what to do for now?

Answer:  Encapsulate it.

So, I want an AC source ...

In spice mode:

.subckt vac (p n)
Vac (p n) AC {ac}
.ends

Now you can use it in any language.

Spice:
X1 (1 2) vac ac=5

Spectre:
V12 (1 2) vac ac=5

Verilog:
vac (.ac(5)) V12 (1, 2);

or..
vac (.ac(5)) V12 (.p(1), .n(2));