New convergence failure (was Re: Several problems: convergence failure...)
Rubén Gómez Antolí <[email protected]> Mon, 01 Mar 2010 14:41:10 +0100
| Newsgroups | gmane.comp.gnu.gnucap.general |
|---|---|
| Message-ID | <[email protected]> |
Hello all:
Sorry about repeat topic, but I'd fall in a nightmare with this circuit
and his evolution.
If is possible that there are a fail in design because I haven't correct
output of buck chopper (1.5 V instead 1V, Ngspice runs circuit :-/ ),
but I can't found the "bug".
I note that in Ngspice output there are too much "noise", that I think
is no normal.
al davis escribió:
> On Friday 05 February 2010, Rubén Gómez Antolí wrote:
>> (...)
>> 2· Convergence failure:
>>
>> gnucap> print tran v(*) i(l1)
>> gnucap> tran 0 5ms 1u > S01.dat
>> non-recoverable convergence failure, reducing (itl4)
>> newtime=8.500000e-05 rejectedtime=8.500001e-05
>> oldtime=8.500000e-05 using=8.500000e-05
>> tried everything, still doesn't work, giving up
>>
>> I'm tried setting itl4 bigger and smaller without sucess.
>
> Looking at the netlist, I see some points that are always
> trouble prone. Some of the component values are unreasonable.
> Changing to more realistic values should fix the problem. This
> is common when using idealized devices.
>
> In particular, your switch specifies ron=0.01 and roff=10Meg.
> This is a ratio of 10^9, which is asking for trouble.
Switch is now a Mosfet (IRF504N).
> Another factor is the rise and fall times of VG, 1p,
> particularly when combined with the option dtmin, which has a
> default value of 1p.
>
> The value of dtmin should be much smaller than the shortest time
> you care about.
>
> Non-recoverable convergence errors in transient analysis are
> usually caused by a bifurcation in the response of a circuit.
> In this case, you have a switch driven by a fast changing
> signal, and settings that do not allow sufficient resolution in
> time, so it alternates between on and off. You need to either
> make VG slower or dtmin faster. Since I doubt if your circuit
> really has 1 ps response, I recommend making VG slower by
> setting rise and fall to something close to what a real circuit
> does.
Circuit evolution to a control commutation circuit driven by a LM311,
which detect zero tresspasing of a triangle wave.
I examined detailed the triangle wave, dtmin and change diode model for
test. No success. I don't have idea where should be the problem.
Here are the circuit:
************************************** Circuit *************************
* Convertidor reductor CC/CC - Practica 4
* gnetlist -v -g spice-sdb -o Convertidor_CC_CC_reductor.cir
Convertidor_CC_CC_reductor.sch
*********************************************************
* Spice file generated by gnetlist *
* spice-sdb version 4.28.2007 by SDB -- *
* provides advanced spice netlisting capability. *
* Documentation at http://www.brorson.com/gEDA/SPICE/ *
*********************************************************
*vvvvvvvv Included SPICE model from ../Macromodelos/LM311.301.cir
vvvvvvvv
* LM311 VOLTAGE COMPARATOR "MACROMODEL" SUBCIRCUIT
* CREATED USING PARTS VERSION 4.03 ON 03/07/90 AT 08:15
* REV (N/A)
* CONNECTIONS: NON-INVERTING INPUT
* | INVERTING INPUT
* | | POSITIVE POWER SUPPLY
* | | | NEGATIVE POWER SUPPLY
* | | | | OPEN COLLECTOR OUTPUT
* | | | | | OUTPUT GROUND
* | | | | | |
.SUBCKT LM311 1 2 3 4 5 6
*
F1 9 3 V1 1
IEE 3 7 DC 100.0E-6
VI1 21 1 DC .45
VI2 22 2 DC .45
Q1 9 21 7 QIN
Q2 8 22 7 QIN
Q3 9 8 4 QMO
Q4 8 8 4 QMI
.MODEL QIN PNP(IS=800.0E-18 BF=500)
.MODEL QMI NPN(IS=800.0E-18 BF=1002)
.MODEL QMO NPN(IS=800.0E-18 BF=1000 CJC=1E-15 TR=102.5E-9)
E1 10 6 9 4 1
V1 10 11 DC 0
Q5 5 11 6 QOC
.MODEL QOC NPN(IS=800.0E-18 BF=103.5E3 CJC=1E-15 TF=11.60E-12
TR=48.19E-9)
DP 4 3 DX
RP 3 4 6.667E3
.MODEL DX D(IS=800.0E-18)
*
.ENDS
*^^^^^^^^ End of included SPICE model from
../Macromodelos/LM311.301.cir ^^^^^^^^
*
*vvvvvvvv Included SPICE model from ../Macromodelos/IRF540N.cir
vvvvvvvv
*SRC=IRF540N;IRF540N;MOSFETs N;Power <=100V;100V 33A .052ohm IR
*SYM=POWMOSN
.SUBCKT IRF540N 1 2 3
* External Node Designations
* Node 1 -> Drain
* Node 2 -> Gate
* Node 3 -> Source
M1 9 7 8 8 MM L=100u W=100u
* Default values used in MM:
* The voltage-dependent capacitances are
* not included. Other default values are:
* RS=0 RD=0 LD=0 CBD=0 CBS=0 CGBO=0
.MODEL MM NMOS LEVEL=1 IS=1e-32
+ VTO=3.55958 LAMBDA=0.000888191 KP=28.379
+ CGSO=1.23576e-05 CGDO=1.77276e-08
RS 8 3 0.0251193
D1 3 1 MD
.MODEL MD D IS=1.13149e-09 RS=0.0078863 N=1.32265 BV=100
+ IBV=0.00025 EG=1.17475 XTI=3.00167 TT=0
+ CJO=7.95433e-10 VJ=0.5 M=0.374991 FC=0.5
RDS 3 1 4e+06
RD 9 1 0.00623556
RG 2 7 4.10175
D2 4 5 MD1
* Default values used in MD1:
* RS=0 EG=1.11 XTI=3.0 TT=0
* BV=infinite IBV=1mA
.MODEL MD1 D IS=1e-32 N=50
+ CJO=1.75616e-09 VJ=0.513551 M=0.614054 FC=1e-08
D3 0 5 MD2
* Default values used in MD2:
* EG=1.11 XTI=3.0 TT=0 CJO=0
* BV=infinite IBV=1mA
.MODEL MD2 D IS=1e-10 N=0.40002 RS=3e-06
RL 5 10 1
FI2 7 9 VFI2 -1
VFI2 4 0 0
EV16 10 0 9 7 1
CAP 11 10 3.86673e-09
FI1 7 9 VFI1 -1
VFI1 11 6 0
RCAP 6 10 1
D4 0 6 MD3
* Default values used in MD3:
* EG=1.11 XTI=3.0 TT=0 CJO=0
* RS=0 BV=infinite IBV=1mA
.MODEL MD3 D IS=1e-10 N=0.40002
.ENDS
*^^^^^^^^ End of included SPICE model from ../Macromodelos/IRF540N.cir
^^^^^^^^
*
*============== Begin SPICE netlist of main design ============
* Fuente de entrada
Vi 60 0 5V
C1 0 50 2200uF
R1 60 50 1
*
* Mosfet como interruptor
X1 50 20 80 IRF540N
* Diodo
D1 0 80 UF4002
* Filtro
C2 0 70 47uF
L1 80 70 1mH
* Carga
RL 0 70 10
*
* Control de conmutación.
*
* CONNECTIONS: NON-INVERTING INPUT
* | INVERTING INPUT
* | | POSITIVE POWER SUPPLY
* | | | NEGATIVE POWER SUPPLY
* | | | | OPEN COLLECTOR OUTPUT
* | | | | | OUTPUT GROUND
* | | | | | |
X2 0 10 30 40 20 0 LM311
*
* Control de conmutación. Onda triangular
.param periodo={1/20kHz}
.param subida={periodo/2}
.param bajada={periodo/2}
VG 10 0 pulse -2.5 5 0 {subida} {bajada} 0.1us {periodo}
* Fuentes de alimentación LM311
V1 30 0 15V
V2 0 40 15V
*Resistencia control de conmutación
R2 30 20 1K
* Modelos
.model UF4004 D (IS=0.65n n=2 TT=50n VJ=0.85 CJO=31.61p MJ=0.33 EG=1.11
BV=400 IBV=10)
.include Campo_de_pruebas/UF4002.model
.tran 1us 30ms
.end
***************************** End of circuit *********************
UF4002 model:
http://www.vishay.com/docs/88183/uf4002.txt
(About how to create a correct UF4004 model, I ask in gEda list.)
Gnucap version (10.Nov.2009):
Gnucap 2009.02.02 RCS 26.109
************ Gnucap output ****************
gnucap> get Convertidor_CC_CC_reductor.ckt
* Convertidor reductor CC/CC - Practica 4
gnucap> option dtmin=0.01p
gnucap> print tran v(*) i(l1)
gnucap> tran 0 30ms 1us > z
@@@unreachable:u_limit.h:109:fet_limit_vgs
@@#
@@@unreachable:u_limit.h:109:fet_limit_vgs
@@#
@@@unreachable:u_limit.h:109:fet_limit_vgs
@@#
@@@unreachable:u_limit.h:109:fet_limit_vgs
@@#
@@@unreachable:u_limit.h:109:fet_limit_vgs
@@#
@@@unreachable:u_limit.h:109:fet_limit_vgs
@@#
(...)
@@#
@@@unreachable:u_limit.h:109:fet_limit_vgs
non-recoverable convergence failure, reducing (itl4)
newtime=8.427083e-06 rejectedtime=8.427083e-06 oldtime=8.427083e-06
using=8.427083e-06
tried everything, still doesn't work, giving up
************ End of gnucap option ****************
Try change itl4 don't alter output, well with itl4=1 I don't have these
fet problems.
Thanks in advance.
Salud y Revolución.
Lobo.
Ps: I try to solve this problem reading and looking for it, ask in mail
list is, always, my last bullet. I'm need to say, I'm felt bad.
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