Re: New convergence failure (was Re: Several problems: convergence failure...)

Hello Al:

al davis escribió:
> On Monday 01 March 2010, Rubén Gómez Antolí wrote:
>> Sorry about repeat topic, but I'd fall in a nightmare with
>>  this circuit  and his evolution.
>>
>> If is possible that there are a fail in design because I
>>  haven't correct  output of buck chopper (1.5 V instead 1V,
>>  Ngspice runs circuit :-/ ), but I can't found the "bug".
>>
>> I note that in Ngspice output there are too much "noise",
>>  that I think  is no normal.
>>
> 
> I can't run it .. there are pieces missing.

Perhaps I should attach it instead do inline. :-/

> Spice time step control and convergence checking is often not 
> strict enough.  Sometimes it accepts results that are wrong.
> 
> Here are a few ideas ...
> 
> Breakdown doesn't work with the native diode model.  Try the one 
> in models-spice3f5 instead and see if that helps.

Well, seems that I fall in troubles too with models:

----------------- Console cut ----------
gnucap> load /usr/share/gnucap/lib/models/spice3f5/dio.so
load /usr/share/gnucap/lib/models/spice3f5/dio.so
      ^ ? /usr/share/gnucap/lib/models/spice3f5/dio.so: undefined 
symbol: _ZN4CARD16set_port_by_nameERSsS0_
gnucap> load /usr/share/gnucap/lib/models/spice3f5/res.so
load /usr/share/gnucap/lib/models/spice3f5/res.so
      ^ ? /usr/share/gnucap/lib/models/spice3f5/res.so: undefined 
symbol: _ZN4CARD16set_port_by_nameERSsS0_
gnucap> load /usr/share/gnucap/lib/models/jspice-2.5/dio.so
load /usr/share/gnucap/lib/models/jspice-2.5/dio.so
      ^ ? /usr/share/gnucap/lib/models/jspice-2.5/dio.so: undefined 
symbol: _ZN4CARD16set_port_by_nameERSsS0_
gnucap> load /usr/local/gnucap/lib/models/bsim/bsim3
bsim301.so  bsim310.so  bsim320.so  bsim321.so  bsim322.so  bsim323.so 
bsim324.so  bsim330.so
gnucap> load /usr/local/gnucap/lib/models/bsim/bsim301.so
load /usr/local/gnucap/lib/models/bsim/bsim301.so
      ^ ? /usr/local/gnucap/lib/models/bsim/bsim301.so: undefined 
symbol: _ZN4CARD16set_port_by_nameERSsS0_
------------------- End of console cut -------------

I supposed that dio.so is correct:

file /usr/share/gnucap/lib/models/spice3f5/dio.so
/usr/share/gnucap/lib/models/spice3f5/dio.so: ELF 32-bit MSB shared 
object, PowerPC or cisco 4500, version 1 (SYSV), dynamically linked, 
with unknown capability 0x41000000 = 0x11676e75, with unknown capability 
0x10000 = 0x90401, stripped


I'm viewing that I lost last snapshot tarball; I'll try to compile 
gnucap and extra models tomorrow.

> Try "option noincmode nobypass".

No sucess.

> Try setting gmin larger.

Fails, stop simulation at certain time:

gnucap> options gmin 2u
gnucap> tran 0 15ms 1us > Salida_S0.dat

tail -n1 Salida_S0.dat
  924.E-6    4.9395     4.7        11.158     15.


> Try adding a resistor across the diodes.
> 
> Try adding a switch, with the control port across a pair of 
> nodes that you think are causing trouble.  Leave the output 
> (switched resistor) unconnected.

I check tomorrow this two, today is too late.

> Try "option method=euler" 
> or "option method=gear"

Fails both:

gnucap> option method=euler
gnucap> print tran v(*) i(l1)
gnucap> tran 0 15ms 1us > Salida_S0.dat
non-recoverable convergence failure, reducing (itl4)
newtime=9.001140e-06  rejectedtime=9.001141e-06  oldtime=9.001139e-06 
using=9.001140e-06
tried everything, still doesn't work, giving up
gnucap> option method=gear
gnucap> tran 0 15ms 1us > Salida_S0.dat
non-recoverable convergence failure, reducing (itl4)
newtime=4.100000e-05  rejectedtime=4.100000e-05  oldtime=4.100000e-05 
using=4.100000e-05
tried everything, still doesn't work, giving up

Still trying, I have hope. Thanks for your effort.

Salud y Revolución.

Lobo.
-- 
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para no atar mis manos con las cadenas del soft propietario.
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