Re: Re[2]: Verilog-A(MS) & gnucap
Leandro Marsó <[email protected]> Wed, 9 Feb 2011 12:30:48 -0300
| Newsgroups | gmane.comp.gnu.gnucap.general |
|---|---|
| Message-ID | <[email protected]> |
2011/2/9 <[email protected]>: > Hello Leandro, > > > from what I saw in available sources, likely "input" and "output" are not > implemented. > > What I saw - you can use "inout" and define nodes, not ports. > > so - pls try: > > module vamp (in, out) ; > inout in, out ; > electrical in, out ; > > ... > V(out) <+ GAIN_V * V(in) ; > ... > > regards > Gena Hi Gena, I've tried that but it yields exactly the same error. Thank you anyway. Best regards, Leandro