Custom Verilog-A model with NGSpice, stack error
"brettf" <[email protected]> Fri, 26 Oct 2012 12:54:27 -0700
| Newsgroups | gmane.comp.gnu.gnucap.general |
|---|---|
| Message-ID | <[email protected]> |
Hi all,
>
> I'm having a problem compiling my custom verilogA file into NGSpice.
> I can't really find any documentation on the XML files (which is where
> my problem is). Lets start with my additions:
>
> --- Added to ngspiceVersion.xml -----
>
> <admst:when test="[name='vco']">
> <admst:if test="[nilled(variable[name='I'])]">
> <admst:value-of select="analog"/>
> <admst:value-of select="."/>
> <admst:new datatype="variable" arguments="%p,I,%p">
> <admst:push into="module/variable" select="." onduplicate="ignore"/>
> <admst:value-to select="sizetype" value="scalar"/>
> <admst:value-to select="type" value="integer"/>
> <admst:value-to select="input" value="yes"/>
> <admst:value-to select="output" value="yes"/>
> <admst:value-to select="parametertype" value="model"/>
> <admst:value-to select="scope" value="global_model"/>
> <admst:new datatype="number" arguments="1">
> <admst:value-to select="scalingunit" value="1"/>
> <admst:value-of select="."/>
> <admst:value-of select="../module"/>
> <admst:new datatype="expression" arguments="%p,%p">
> <admst:value-of select="."/>
> <admst:value-to select="../../default" value="%p"/>
> </admst:new>
> </admst:new>
> </admst:new>
> </admst:if>
> </admst:when>
>
> What are these functions? Is there any explanation as to how to use
> them or do we just blindly copy and paste when adding new files?
>
> ----- wrapper.h file I've added for my verilog file ----
>
> extern "C" {
> #include "vcodefs.h"
> }
>
> #define info vcoinfo
> #define INSTANCE vcoinstance
> #define MODEL vcomodel
>
> #define SPICE_LETTER "I"
> #define DEVICE_TYPE "ngspice_vco"
> #define MIN_NET_NODES 2
> #define MAX_NET_NODES 2
> #define INTERNAL_NODES 0
> #define MODEL_TYPE "Ivco|I"
>
>
> static std::string port_names[] = {"in", "out"};
> static std::string state_names[] = {};
>
> /*
> */
> Am I missing something here? Any explanations as to what needs to be
> in here?
>
> And finally, my vco.va file:
>
> `include "discipline.h"
> `include "constants.h"
> module vco(in,out);
> inout in,out;
> // output out;
> electrical in,out;
> // SJM added
> //voltage vin;
>
> parameter real f0 = 1.0M from [0:inf], // center frequency
> kf = 100e03, // frequency coefficient Hz/V
> lockrange = 3, // lockrange according input
> voltage
> vin_offset = 0, // input dc offset, e.g.
> V(in)=vin_offs et -> f0
> vout_offset = 0, // output dc offset
> vout_mag = 3, // output magnitude
> phi0 = 0, // dc phase, given in radian
> vin = 0;
>
> real w;
>
> analog begin
> begin
> vin = V(in) - vin_offset;
> if (vin > lockrange) vin = lockrange;
> else
> if (vin < -lockrange) vin = -lockrange;
>
> w = 0.63661977236758134308*(f0 + kf*vin);
> V(out) <+ vout_offset + vout_mag*sin(w*$realtime + phi0);
> end
> end
> endmodule
>
> When I'm trying to compile, I'm getting the following error in the
> console:
>
> [fatal..] stack '%s' has no more element!
> [fatal..] see [../admst/ngspiceMODULE.hxx.xml:2504]make: *** [vco.c]
> Error 1
>
> I can't find anything on Google or this mailing list for this error.
> Any and all help is appreciated. Thanks.
>
> Brett