Re: parameter usage in simulatoin

On Sun, Apr 19, 2020 at 4:45 PM Felix Salfelder <[email protected]> wrote:
>
> On Sun, Apr 19, 2020 at 04:16:17PM +0200, patrick wrote:
> > I am trying to vary W/L parameters of a MOS transistor.
>
> Hi Patrick.
>
> Could you share the model or instanciation of that transistor?

Hi Felix,

thanks for the pointers.
My goal is to get/refresh some basic understanding of simple circuits.
As a start I take this inverter where I would like to sweep W/L
parameters. Indeed W and L would be on the global scope (I think it's
what works in other simulators - but not so important):

.param wn=1
.param wp=2

.subckt inv inn outn vddn
  m2 outn inn vddn vddn  pmos1  w=wp
  m1 outn inn 0       0  nmos1  w=wn
.ends

# supply voltage
vdd  inv_vdd1 0  DC  5

# inverter
x1 inv_in out_n inv_vdd inv

# load
rds  inv_vdd1 inv_vdd  1e-6

# inverter input
vin  inv_in 0  DC  3

.model nmos1 nmos
.model pmos1 pmos

.print dc v(out_n)

.dc vin 0 5 0.2



Note: The "module" syntax is interesting because I also started to
use/learn verilog. And a common syntax might be nice. However, the
example of the resistor module gives:

default plugins: cmake-2 2017.10.18

module m(1,2);
       ^ ? need 4 more nodes
module m(1,2);
           ^ ? no match: area
resistor #(.r(w*5)) r(1,2);
             ^ ? need )
resistor #(.r(w*5)) r(1,2);
                  ^ ? what's this?
resistor #(.r(w*5)) r(1,2);
                    ^ ? what's this?
resistor #(.r(w*5)) r(1,2);
                          ^ ? what's this?
endmodule
          ^ ? need 4 more nodes


Surely I am missing some things... anyway thanks for your help.