Re: geda/lepton schematics

Felix:
...
> A subsheet is essentially a subcircuit macro. It exists in spice
> (.subckt) and in Verilog ("module" with sub-components), and in the
> others as well.
>
> Such a macro has ports, internal nets, parameters and a list of
> components + the connectivity (!). Much the same as a schematic
> subsheet, just without the positions.
...

Soo,
 every sym file is a module
 every sch file is a module
 you only need to find out the implicit nets within the sch file
  not for the whole system

and you could basically make, as a cache, verilog files of every
sch/sym file you have, and later only update the subsheet references.

Hälsningar,
/Karl Hammar

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