strange behavior with makefile

Hi,

I am just before getting mad with that makefile. I already shortened my
large makefile to just a few lines:

*makefile:*

TARGET = TEST

SRC_DIR   = ..\src
OUT_DIR   = ..\out
TMP_DIR   = ..\tmp

vpath %.c	$(SRC_DIR)
	
# Compiler
CC = ..\..\tools\compiler\cx6808
	
CFLAGS = -pp -vl +nowiden +debug -oc -co$(TMP_DIR) -cl$(OUT_DIR)

C_FILES_APP = bootload.c can.c

H_FILES_APP = bootload.h 

OBJ_FILES = $(C_FILES_APP:.c=.o)


FIRST: $(TARGET).s19


all: h08 s19

h08: $(TARGET).h08
s19: $(TARGET).s19

$(TARGET).h08: $(OBJ_FILES)



*Call from command shell:*
..\..\tools\make\make -n -s -f makefile all


*Output:*
..\..\tools\compiler\cx6808 -pp -vl +nowiden +debug -oc -co..\tmp -cl..\out  
-c -o bootload.o ..\src/bootload.c
..\..\tools\compiler\cx6808 -pp -vl +nowiden +debug -oc -co..\tmp -cl..\out  
-c -o can.o ..\src/can.c
make: *** No rule to make target `TEST.s19', needed by `s19'.  Stop.



Why does make indicate that it wants to make a compiler call and why with
those options -c -o and why is there a / instead of a \ ???

Can anybody help me?

Thank you!

Uwe




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