Re: plotting transfer function in octave 5.2: How to fix error: set: "dataaspectratio' must be finite
Torsten Lilge <[email protected]>
| Newsgroups | gmane.comp.gnu.octave.general |
|---|---|
| Message-ID | <[email protected]> |
On Fri, 2020-08-07 at 22:06 +0300, Sergei Steshenko via Help-octave wrote: > On 07/08/2020 18:31, shall689 wrote: > > Hello Torsten, > > > > > If you consider the complete control loop in discrete time (the > > > system > > > has to be discretized), then you do not need any transfer function > > > for > > > your hold device. Instead, it is considered in the calculation of > > > the > > > discrete time system representation. If, e.g., the used D/A has a > > > zero- > > > order hold, than the discretization method makes use of the fact > > > that > > > the input u is constant during a sampling interval. > > Yes, if I use the ZOH method when discretizing, the ZOH will be > > included. > > > > What if there are two feedbacks, i.e a voltage and a current > > feedback (see > > diagram below)? Should the ZOH be placed in both loops as shown in > > the > > second diagram? My system is sampling all feedbacks at the same > > time, so > > there is essentially only one delay; however, I think two zero order > > holds > > would add two delays. > > > > Stephen > > > > < > > https://octave.1599824.n4.nabble.com/file/t372348/TwoLoopControlDiagram.jpg > > > > > > > < > > https://octave.1599824.n4.nabble.com/file/t372348/TwoLoopControlDiagramWithZOH.jpg > > > > > > > > > > > -- > > Sent from: > > https://octave.1599824.n4.nabble.com/Octave-General-f1599825.html > > > > > "I think two zero order holds would add two delays" - before deciding > on > adding delays think about the following. One delay stage adds 2 * pi > * > delay / frequency phase shift, where 'frequency' is the frequency at > which you want to know phase shift. > > In a control system magnitude and phase plots the most important area > is > the area in which magnitude response is about 0db - this is where one > looks at phase margin. Let's call this frequency frequency_0db. So, > if > frequency_0db is much less than sample rate, then one sample delay > introduces negligible phase shift. > > --Sergei. > One of the most common misunderstandings when doing discrete-time control is, that ZOH aren't really "added" to the control. In general, a D/A converter *is* a ZOH and has to be modeled as such. You have a cascaded control with the voltage control in the outer loop, right? Then G2 is a discrete-time controller and its output is the setpoint for the inner, namely the current controller (also discrete- time). This, the real, continous-time system is H1, H2, F1, and F2. Is this correct? When considering the complete control loop in discrete-time, you have ZOH1 as a real D/A converter. You would have to discretize the systems ZOH1-H1-F1 and ZOH1-H1-H2-F2 and you can represent the complete comtrol loop in discrete-time. Torsten