$(wildcard) with Make

I have a makefile that builds a compiler, then compiles a number of
test programs to instructions for Jasmin (assembler for the JVM), then
assembles them by calling Jasmin. The makefile currently does something
like this:

$(foreach f, $(tests), java Compile $f &&) echo "Compiled tests
successfully"
$(foreach f, $(wildcard *.j), jasmin $f &&) echo "Assembled tests
successfully"

The crucial problem here is with $(wildcard *.j), which apparently
expands to an empty string unless the matching files are present in the
directory before Make is invoked (not before that line is executed, as
I expected). I can run make a 2nd time to get around the problem, but
obviously this is not ideal. Is anyone out there a Make guru who can
suggest a good way for me to get this behavior without ugly kludges
(and without listing all the input and target files in the makefile)?

I thought about doing this:

$(foreach f, $(addsuffix .j,$(basename $(notdir $(tests)))), jasmin $f
&&) echo "Compiled tests successfully"

but unfortunately, the input files don't have the same basename as the
output files, and often the names are unrelated.

Thanks,
Nate