Make: puzzeling make behaviour ?

Hi,

I am trying to compile a simple program that use a static library in
~/lib with corresponding include file in ~/include. My LD_LIBRARY_PATH
includes ~/lib. Here is the Makefile

------------------------------------------------------------------
CC=gcc
GLLIB=-lGL
GLULIB=-lGLU
GUILIBS=-L/usr/X11R6/lib -lX11
OTHRLIBS=-lm
GLTKPATH=/home/bt
GLTKLIB=-L$(GLTKPATH)/lib -lgltk
GLTKINC=-I$(GLTKPATH)/include

CFLAGS=$(GLTKINC)
LDFLAGS=$(GUILIBS) $(GLLIB) $(GLULIB) $(OTHRLIBS) $(GLTKLIB)

SRCFILES=$(wildcard *.c)
OBJFILES=$(patsubst %.c,%.o, $(SRCFILES))
PROGRAMS=$(patsubst %.c,%, $(SRCFILES))

build:  $(PROGRAMS)
	$(CC) $(CFLAGS) $(LDFLAGS) -o "$@" "$<"
	
clean:
	rm -f $(PROGRAMS)
-------------------------------------------------------------------

However the compilation fails even though all the paths in this makefile
are correct, gcc can not find symbols defined in libgltk.a . Also
if I try to change the gcc command line and then run make again it 
does not run the changed version of the command !!! I am baffled.
For instance if I surround the LDFLAGS argument with -Wl, --startgroup
and -Wl, --endgroup and run make, these don't appear in the echoed
command line. Of for that matter if I change the order of any of the 
gcc arguments, on executing make the changed order is not reflected
in the echoed command line. In my working directory I only have two
files : a c program and the Makefile. My make version is 3.80 and
gcc version is 3.3.5 and I am using Debian/Sarge. Using vim's
"set list" feature I can ensure there are not extraneous characters
in the make file and tabs/newlines are where they should be.

Would be grateful for you suggestions.

regards
b thomas