Help about "Include" in Makefile

I have write a makefile like this:

OBJS = $(patsubst %.cpp ,%.o,$(CPP))
DEPS = $(patsubst %.cpp ,%.d,$(CPP))

all : $(OBJS) $(DEPS)

%.o : %.cpp
...

%.d : %.cpp
...

-include $(DEPS)

clean:
    rm -f $(OBJS)
    rm -f $(DEPS)

we do make it will first generate the depend files (.d files);

but when i do make clean, it also generate depend file before doing
clean. what can i do to avoid this uncessary

operation!