Re: libpng: Add support for RISC-V Vector Extension

Hello,

just a quick reminder that this is still waiting for integration.
More Details: https://github.com/mschlaegl/libpng_rvv-doc/blob/main/README.md
There is also a pull request on github:
https://github.com/glennrp/libpng/pull/405

FYI: In the meantime, a paper on RVVRadar (including results of PNG
filter optimization for RISC-V Vector) has been published. RVVRadar
helps programmers in vectorizing applications for RISC-V Vector.
It was presented this week at the GLSVLSI 2022.
https://www.ics.jku.at/files/2022GLSVLSI_RVVRadar.pdf

Sincerely,
Manfred


On 16.12.21 15:19, Manfred Schlaegl wrote:
> Hello,
>
> The long awaited RISC-V Vector Extension (RVV) is finally in
> ratification.[1] The attached patches for libpng16 add support
> for RVV optimized png filter types to libpng:
>  * 0001-INSTALL-added-missing-contrib-content.patch
>    * Contains a simple fix in INSTALL but is necessary for
>      applying the main patch
>  * 0002-libpng-Add-support-for-RISC-V-Vector-Extension.patch
>    * Support for RISC-V Vector Extension
>
> There is also a fork on github: https://github.com/mschlaegl/libpng_rvv
>
>
>
> Development and performance evaluation of the filter type
> implementations (up, sub, avg and paeth) was done on Allwinner D1 with
> RVV 0.7.1 using RVVRadar. Details on that can be found in an article
> published on github.[2]
>
> The integration in libpng was done very similarly as for other
> architectures (ARM NEON, MIPS MSA, ...): There exists a configure
> switch "riscv-vector" which can be set to no/off, check, api, yes/on.
> And there is also run-time checking code (like for ARM NEON,
> MIPS MSA, ...).
>
> More important are the differences:
>  1. We introduce a separate configure switch "riscv-vector-compat"
>  2. We use inline assembler instead of compiler intrinsics
>
> Both is done for the same reason: To support multiple RVV versions.
>
> As mentioned above, RVV 1.0 is under ratification now. But there are
> earlier draft versions which are sporadically already implemented in
> real existing hardware. One example is the Allwinner D1 with RVV 0.7.1
> which was used for performance evaluation and optimization of these
> filter implementations.[2] We therefore decided to support the
> following RVV versions: 0.7.1, 0.8, 0.9, 0.10 and 1.0.
>
> Unfortunately, there is no easy way to detect the RVV version
> supported by the toolchain. It was therefore necessary to add an
> additional configure switch "riscv-vector-compat" with following
> behavior:
>  * not-set/off(default): RVV release 1.0
>  * set to "0.10": RVV draft 0.10
>  * set to "0.9": RVV draft 0.9
>  * set to "0.8": RVV draft 0.8
>  * set to "0.7.1": RVV draft 0.7.1
>
> Furthermore compiler intrinsics were not available for all supported
> RVV versions. For this reason we had to use inline assembler instead
> of compiler intrinsics.
>
> The filter implementations for all supported RVV versions were tested
> in the following setups:
>
>  RVV     | Branch of              | Test system
>  Version | riscv-gnu-toolchain[3] |
> ---------------------------------------------------------------------
>  1.0     | "basic-rvv"            | qemu_sifive [4]
>  0.10    | "rvv-intrinsic"        | qemu_sifive [4]
>  0.9     | "rvv-0.9.x"            | Allwinner D1 (binary compatible)
>  0.8     | "rvv-0.8.x"            | Allwinner D1 (binary compatible)
>  0.7.1   | "rvv-0.7.1"            | Allwinner D1 (RVV 0.7.1)
>
> References:
> -----------
> [1] https://riscv.org/announcements/2021/12/riscv-ratifies-15-new-specifications/
> [2] https://github.com/mschlaegl/libpng_rvv-doc/blob/main/README.md
> [3] https://github.com/riscv-collab/riscv-gnu-toolchain
> [4] https://github.com/sifive/qemu/tree/rvv-1.0-upstream-v10
>
>
>
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