Re: bootloader and framebuffer

//
// THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
// ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
// PARTICULAR PURPOSE.
//
// Copyright (c) 1999 MediaQ, Inc.
//
//#include <windows.h>
//#include <tchar.h>


#include "mqhw.h"
#include "mq200.h"
#include "misc.h"

//#define DUMP_REG

#define Sleep(a) udelay(a*1000)
int rand(void);
int display_on(int on);
void gen_pattern(void);

#define Random() rand()


// Prototypes
//
void writeBrightness(int brightness);
void FindPhysicalAddr(void);
int MapAddr(void);
unsigned long CheckID(void);
void ConfigDisplay(void);
void InitChip(void);
void SetupLCD(void);
void SetupCRT(void);
void SetupDAC(void);
PMQ_TIMING_PARAM GetMQTiming(USHORT,USHORT,USHORT);
void GetMQPLL(float,unsigned long*);
int InVBlank(void);
void do_blt(void);
void panel_demo(void);
void crt_demo(void);
void rfill(unsigned long x, unsigned long y,
unsigned long dx, unsigned long dy, unsigned long colour,unsigned long rop);
void rfill2(unsigned long x, unsigned long y,
unsigned long dx, unsigned long dy, unsigned long colour,unsigned long rop);
void s2s(unsigned sx,
			unsigned int sy,
			unsigned int dx,
			unsigned int dy,
			unsigned int w,
			unsigned int h,
			unsigned int rop);
void CleanUp(void);
void gen_lines(void);
void test_brightness(void);

#ifdef CHECK_GE_NOTBUSY
void WaitGENotBusy(void);
#endif	//CHECK_GE_NOTBUSY
#ifdef CHECK_CMDFIFO
void WaitCmdFIFO(ULONG);
#endif	//CHECK_CMDFIFO
#ifdef CHECK_SRCFIFO
void WaitSrcFIFO(ULONG);
#endif	//CHECK_SRCFIFO



// Global data
//
char		*m_pMMIO;			// Pointer to memory-mapped register space
char		*m_pFB;				// Pointer to frame buffer address
unsigned long		ulPhysicalMMIO;	// Physical address of mmio
unsigned long		ulPhysicalFB;		// Physical address of frame buffer
unsigned long		ulPLL2, ulPLL3;
DISPLAY_CONFIG dspconfig;	// Display configuration
PFP_CONTROL_STRUC	m_pFPControl;		//Pointer to active FP structure
PMQ_TIMING_PARAM	m_pCRTTiming;		//Pointer to timing for CRT


void  CHECK_IF_STATE_D( s )			 
 {                                               
   unsigned long   ulState  = (s);               
   unsigned long   ulPMReg;			 
                                                 
   while (1)                                   	 
   {                                             
      ulPMReg = pciREAD(PCI_PM_CNTL_STATUS);	 
		if ((ulPMReg & 0x03L) == ulState)
			break;			 
   }                                             
 }


int ulID=0;

//
// Main program entry point ...
//
int setup_mq200 (void)
{

	// *(long *)0xa000002c=0x42194449;	
	printf("MSC2=0x%08lx :: ", *(long *) 0xa000002c);	
	FindPhysicalAddr();
#if MAP_DEVICE 
	if (!MapAddr())
	{
		printf("MapAddr Fail ...\r\n");
		return FALSE;
	}
#endif
	ulID = CheckID();
	if (ulID != MQ200_DEVICE)
	{
		printf("Read back MQ200 ID is %08x ...\r\n",ulID);
		printf("Correct Device ID should be 0x02004D51.\r\n");
		return FALSE;
	}
	ConfigDisplay();
	InitChip();	
	// do_blt();
	gen_pattern();
	gen_lines();

	writeBrightness(128);
#if 0
	test_brightness();
#endif	
#if MAP_DEVICE 
	CleanUp();
#endif
   return (TRUE);
}


//
// SH3 7709 and SH4:
//		0x93800000L
// TX3922:
//		0x6D800000L
// SA1110:
//		0x1B800000L (nCS[3])
//		0x43800000L (nCS[4])
//		0x4B800000L (nCS[5])
// PCI:
//		From PCI configuration space
//

#define FB_BASE		0x4B800000L

void FindPhysicalAddr(void)
{
	m_pFB           = (char *) FB_BASE;
	m_pMMIO         = (char *) FB_BASE + 0x600000L;
	ulPhysicalFB 	= FB_BASE;
	ulPhysicalMMIO	= FB_BASE + 0x600000L;
}

#if MAP_DEVICE
// Map physical address to linear address using system call
// - This will be different depending on target OS ...
//
int MapAddr(void)
{
	BOOL	status = TRUE;

	// Allocate and map memory space for 2MB of frame buffer
	//
	m_pFB = (LPBYTE)VirtualAlloc( 0, FB_SIZE, MEM_RESERVE, PAGE_NOACCESS );
	status = VirtualCopy( m_pFB, (LPVOID)ulPhysicalFB, FB_SIZE,
									PAGE_READWRITE|PAGE_NOCACHE );
	if ( status == FALSE )
		return (FALSE);

	// Allocate and map MQ200 register space 
	//
	m_pMMIO = (LPBYTE)VirtualAlloc( 0, MMIO_SIZE, MEM_RESERVE, PAGE_NOACCESS );
	status = VirtualCopy( m_pMMIO, (LPVOID)ulPhysicalMMIO, MMIO_SIZE,
							 PAGE_READWRITE|PAGE_NOCACHE );
	if (status == FALSE)
		return (FALSE);
		
	return (TRUE);
}
#endif

// This routine return MQ200 PCI vendor ID
//
unsigned long CheckID(void)
{
	return (pciREAD(PCI_VENDOR_DEVICE));
}

// This sample code demonstrates flat panel (LCD) running 800x600x8 mode
// and CRT running 1024x768x16 mode. Graphics Controller 2 (GC2) is used
// to drive LCD and GC1 to drive CRT. GC1 uses PLL2 and GC2 uses PLL3.
// MIU, GE and bus is clocked by PLL1 running 83MHz.
//
// - Memory limitation: (watch out starting boundary)
//		GC1+GC2+DSTN half FB+HW cursor < 2MB
//
void ConfigDisplay(void)
{
	dspconfig.paneltype 	 = 4;	// SVGA TFT (800x600)
	dspconfig.panelbpp 	 = 16 ; //8;	// 16 bits per pixel mode
	m_pFPControl             = &FPControlData[dspconfig.paneltype-1];
	dspconfig.panelstride    = m_pFPControl->usHoriSize * dspconfig.panelbpp / 8;
	dspconfig.panelstartaddr = 0;

	dspconfig.crtx 		= 1024;
	dspconfig.crty 		=  768;
	dspconfig.crtbpp 	=    8;
	dspconfig.crtfreq 	= 70;
	dspconfig.crtstride 	= dspconfig.crtx * dspconfig.crtbpp / 8;
	dspconfig.crtstartaddr  = dspconfig.panelstride * m_pFPControl->usVertSize;
}

///////////////////////////////////////////////////////////////////////
////  Initialization sequence ...
////
////  1. Setup DCR00R -  for bus clock/MIU/GE etc...
////  2. Enter D0 state from reset (D3 state)
////  3. Setup PMU.         
////  4. Setup MIU.        
////  5. Misc registers
////  6. Set up LCD-related registers and PLL - enable it afterwards
////  7. Set up CRT-related registers and PLL - enable it afterwards
///////////////////////////////////////////////////////////////////////
void InitChip(void)
{
	unsigned long ulClassRevID;
	ULONG ulTemp;
	
	// Set up DC00R (PLL1) for BIU, GE and MIU clock - 83MHz
	dcREG(DC_0, MQInitParam.ulDC0);
	Sleep(5);
	pciREG(PCI_PM_CNTL_STATUS, ENTER_D0);
	Sleep(30);
	CHECK_IF_STATE_D(0); 		//Make sure in a stable state

	// Get Revision ID
	ulClassRevID = pciREAD(PCI_REV_CLASS) & 0x000000FF;
	printf("MQ200 - Revision ID=%x ...\r\n",ulClassRevID);

	//Set up PMU misc registers 
	// - also PMCLK_2048CYCLE and FP_PMCLK_128K if SA1110
	pmuREG(PM_MISC, (GE_ENABLE | GE_BY_PLL1) );
	pmuREG(D1_STATE, MQInitParam.ulD1);
	pmuREG(D2_STATE, MQInitParam.ulD2);

	//To initialize MIU bloc:
	//
	miuREG(MIU_CONTROL1, DRAM_RESET_DISABLE);
	Sleep(5);

	miuREG(MIU_CONTROL1, 0x00);
	Sleep(50);

	// Enable auto-refresh for 1B and above ...
	if (ulClassRevID != MQ200_REV_1A)
		MQInitParam.ulMIU2 |= AUTO_REF_ENABLE;

	miuREG(MIU_CONTROL2, MQInitParam.ulMIU2);
	miuREG(MIU_CONTROL3, MQInitParam.ulMIU3);
	// MIU REG 5 MUST BE PROGRAMMED BEFORE MIU REG 4
	miuREG(MIU_CONTROL5, MQInitParam.ulMIU5);
	miuREG(MIU_CONTROL4, MQInitParam.ulMIU4);
	Sleep(50);

	miuREG(MIU_CONTROL1, MIU_ENABLE | MIU_RESET_DISABLE);
	Sleep(50);
	
	//Here, MIU is supposed to ready to serve ...

	fpREG(FP_GPO_CONTROL,	MQInitParam.ulGPO);
	fpREG(FP_GPIO_CONTROL,	MQInitParam.ulGPIO);
	// Set up LCD panel : GC1 clocked by PLL2
	SetupLCD();
	// Set up CRT: GC2 clocked by PLL3
	SetupCRT();
	// Set up Palette
	SetupDAC();
#ifdef DUMP_REG
	ulTemp = dcREAD(DC_0);	//get current setting
	printf("DC0=%x\r\n",ulTemp);
	ulTemp = pmuREAD(PM_MISC);	//get current setting
	printf("PM_MISC=%x\r\n",ulTemp);
	ulTemp = pmuREAD(PLL2_CONTROL);	//get current setting
	printf("PLL2_CONTROL=%x\r\n",ulTemp);
	ulTemp = pmuREAD(PLL3_CONTROL);	//get current setting
	printf("PLL3_CONTROL=%x\r\n",ulTemp);
	ulTemp = miuREAD(MIU_CONTROL2);	//get current setting
	printf("MIU_CONTROL2=%x\r\n",ulTemp);
	ulTemp = miuREAD(MIU_CONTROL3);	//get current setting
	printf("MIU_CONTROL3=%x\r\n",ulTemp);
	ulTemp = miuREAD(MIU_CONTROL4);	//get current setting
	printf("MIU_CONTROL4=%x\r\n",ulTemp);
	ulTemp = miuREAD(MIU_CONTROL5);	//get current setting
	printf("MIU_CONTROL5=%x\r\n",ulTemp);
	ulTemp = gc1READ(GC1_CONTROL);	//get current setting
	printf("GC1_CONTROL=%x\r\n",ulTemp);
	ulTemp = gc2READ(GC2_CONTROL);	//get current setting
	printf("GC2_CONTROL=%x\r\n",ulTemp);
	ulTemp = fpREAD(FP_CONTROL);	//get current setting
	printf("FP_CONTROL=%x\r\n",ulTemp);
	ulTemp = gc1READ(GC1_CRT_CONTROL);	//get current setting
	printf("GC1_CRT_CONTROL=%x\r\n",ulTemp);
	printf("-------------------------------------------\r\n");

	ulTemp = gc1READ(HD1_CONTROL);	//get current setting
	printf("HD1_CONTROL=%x\r\n",ulTemp);
	ulTemp = gc1READ(VD1_CONTROL);	//get current setting
	printf("VD1_CONTROL=%x\r\n",ulTemp);
	ulTemp = gc1READ(HS1_CONTROL);	//get current setting
	printf("HS1_CONTROL=%x\r\n",ulTemp);
	ulTemp = gc1READ(VS1_CONTROL);	//get current setting
	printf("VS1_CONTROL=%x\r\n",ulTemp);
	ulTemp = gc1READ(IW1_STRIDE);	//get current setting
	printf("IW1_STRIDE=%x\r\n",ulTemp);
	ulTemp = gc1READ(IW1_START_ADDR);	//get current setting
	printf("IW1_START_ADDR=%x\r\n",ulTemp);
	
	ulTemp = gc2READ(HD2_CONTROL);	//get current setting
	printf("HD2_CONTROL=%x\r\n",ulTemp);
	ulTemp = gc2READ(VD2_CONTROL);	//get current setting
	printf("VD2_CONTROL=%x\r\n",ulTemp);
	ulTemp = gc2READ(HS2_CONTROL);	//get current setting
	printf("HS2_CONTROL=%x\r\n",ulTemp);
	ulTemp = gc2READ(VS2_CONTROL);	//get current setting
	printf("VS2_CONTROL=%x\r\n",ulTemp);
	ulTemp = gc2READ(IW2_STRIDE);	//get current setting
	printf("IW2_STRIDE=%x\r\n",ulTemp);
	ulTemp = gc2READ(IW2_START_ADDR);	//get current setting
	printf("IW2_START_ADDR=%x\r\n",ulTemp);
	
	ulTemp = fpREAD(FP_CONTROL);	//get current setting
	printf("FP_CONTROL=%x\r\n",ulTemp);
	ulTemp = fpREAD(FP_PIN_CONTROL);	//get current setting
	printf("FP_PIN_CONTROL=%x\r\n",ulTemp);
	ulTemp = fpREAD(FP_GPO_CONTROL);	//get current setting
	printf("FP_GPO_CONTROL=%x\r\n",ulTemp);
	ulTemp = fpREAD(FP_GPIO_CONTROL);	//get current setting
	printf("FP_GPIO_CONTROL=%x\r\n",ulTemp);
	ulTemp = fpREAD(STN_CONTROL);	//get current setting
	printf("STN_CONTROL=%x\r\n",ulTemp);
	ulTemp = fpREAD(DSTN_FB_CONTROL);	//get current setting
	printf("DSTN_FB_CONTROL=%x\r\n",ulTemp);
	ulTemp = fpREAD(PWM_CONTROL);	//get current setting
	printf("PWM_CONTROL=%x\r\n",ulTemp);
#endif
	display_on(1);	
}

// This routine set up GC2 and flat panel registers. LCD is driven by
// graphics controller 2 and uses PLL3 as clock source.
//
void SetupLCD()
{
	unsigned long ulTemp;

	// Set up start address and stride
	gc2REG(IW2_START_ADDR, dspconfig.panelstartaddr);
	gc2REG(IW2_STRIDE, dspconfig.panelstride);

	// Set up LCD Window-related registers
	gc2REG(HW2_CONTROL, (m_pFPControl->usHoriSize - 1) << 16);
	gc2REG(VW2_CONTROL, (m_pFPControl->usVertSize - 1) << 16);

	// Set up LCD timing registers ...
	gc2REG(HD2_CONTROL, m_pFPControl->ulHD);
	gc2REG(VD2_CONTROL, m_pFPControl->ulVD);
	gc2REG(HS2_CONTROL, m_pFPControl->ulHS);
	gc2REG(VS2_CONTROL, m_pFPControl->ulVS);

	// Set up DSTN half frame buffer address
	if (m_pFPControl->ulFPControl & FP_TYPE_DSTN)
	{
		// Color D-STN memory requirement - no need to *3 for mono dstn panel
		unsigned long ulDSTNFBSize = (((m_pFPControl->usHoriSize * 3 + 127) >> 7) *
					 	m_pFPControl->usVertSize) << 3;
	
  		unsigned long	ulScreenSize = dspconfig.panelstride * m_pFPControl->usVertSize +
									dspconfig.crtstride * dspconfig.crty;
  		unsigned long	ulStartAddr = (ulScreenSize + 127) >> 7;
  		unsigned long	ulEndAddr = (ulScreenSize + ulDSTNFBSize + 15) >> 4;
  		fpREG(DSTN_FB_CONTROL, (ulStartAddr | ((ulEndAddr - 1) << 16)));
	}
	
	//Set up the rest of flat panel registers
	fpREG(FP_CONTROL, 		m_pFPControl->ulFPControl);
	fpREG(FP_PIN_CONTROL,	m_pFPControl->ulFPPinControl);
	fpREG(STN_CONTROL,		m_pFPControl->ulSTNControl);
	fpREG(PWM_CONTROL,		m_pFPControl->ulPWMControl);

	//FRC is NOT needed for TFT panel
	if ( (m_pFPControl->ulFPControl & FP_TYPE_MASK) != FP_TYPE_TFT )
	{
		int		i;
		for ( i = 0; i < FRC_PATTERN_CNT; i++ )
  			fpREG((FRC_PATTERN + i * uBUSW), FRCControlData[0].ulFRCPattern[i]);
		for ( i = 0; i < FRC_WEIGHT_CNT; i++ )
  			fpREG((FRC_WEIGHT + i * uBUSW), FRCControlData[0].ulFRCWeight[i]);
	}

	// Use PLL3 to drive LCD
	GetMQPLL( m_pFPControl->fPLLFreq, &ulPLL3);
	pmuREG(PLL3_CONTROL, ulPLL3);
	pmuREG(PM_MISC, pmuREAD(PM_MISC) | PLL3_ENABLE);

	ulTemp = FDx_1 | (1UL << 24)
					| IM_ENABLE
					| GxRCLK_PLL3;
	switch(dspconfig.panelbpp)
	{
		case  8: ulTemp |= GC_8BPP;	break;
		case 16: ulTemp |= GC_16BPP_BP;	break;
		case 24: ulTemp |= GC_24BPP_BP;	break;
		case 32: ulTemp |= GC_32BPP_ARGB_BP;	break;
	}
	gc2REG(GC2_CONTROL, ulTemp);

	// Enable LCD driven by GC2
	//
	ulTemp = fpREAD(FP_CONTROL);
	fpREG(FP_CONTROL, ulTemp|FPI_BY_GC2);

	ulTemp = gc2READ(GC2_CONTROL);
	gc2REG(GC2_CONTROL, ulTemp|GC_ENABLE);
}

// This routine set up GC1 registers. CRT is driven by
// graphics controller 1 and uses PLL2 as clock source.
//
void SetupCRT()
{
	unsigned long ulTemp;

	m_pCRTTiming = GetMQTiming(dspconfig.crtx,dspconfig.crty,dspconfig.crtfreq);

	// Set up start address and stride
	gc1REG(IW1_START_ADDR, dspconfig.crtstartaddr);
	gc1REG(IW1_STRIDE, dspconfig.crtstride);

	// Set up CRT Window-related registers
	gc1REG(HW1_CONTROL, (dspconfig.crtx - 1) << 16);
	gc1REG(VW1_CONTROL, (dspconfig.crty - 1) << 16);

	gc1REG(HD1_CONTROL, m_pCRTTiming->ulHD);
	gc1REG(VD1_CONTROL, m_pCRTTiming->ulVD);
	gc1REG(HS1_CONTROL, m_pCRTTiming->ulHS);
	gc1REG(VS1_CONTROL, m_pCRTTiming->ulVS);
	gc1REG(GC1_CRT_CONTROL, m_pCRTTiming->ulCRTC);

	// Use PLL2 to drive CRT
	GetMQPLL( m_pCRTTiming->fPLLFreq, &ulPLL2);
	pmuREG(PLL2_CONTROL, ulPLL2);
	ulTemp = pmuREAD(PM_MISC) | PLL2_ENABLE;
	pmuREG(PM_MISC,ulTemp);

	ulTemp = FDx_1 | (1UL << 24)
					| IM_ENABLE
					| GxRCLK_PLL2;
	switch(dspconfig.crtbpp)
	{
		case  8: ulTemp |= GC_8BPP;	break;
		case 16: ulTemp |= GC_16BPP_BP;	break;
		case 24: ulTemp |= GC_24BPP_BP;	break;
		case 32: ulTemp |= GC_32BPP_ARGB_BP;	break;
	}
	gc1REG(GC1_CONTROL, ulTemp);

	// Enable CRT driven by GC1
	//
	ulTemp = gc1READ(GC1_CRT_CONTROL);
	gc1REG(GC1_CRT_CONTROL, ulTemp|CRT_BY_GC1);

	ulTemp = gc1READ(GC1_CONTROL);
	gc1REG(GC1_CONTROL, ulTemp|GC_ENABLE);
}

// Return correct CRT timing parameters pointer
//
PMQ_TIMING_PARAM GetMQTiming(USHORT x, USHORT y, USHORT freq)
{
	unsigned int i;
	for (i=0; i < MAX_MQTIMING; i++)
	{
		if ( MQTimingParam[i].usResoX == x
			&& MQTimingParam[i].usResoY == y
			&& MQTimingParam[i].usFreq == freq )
			return ( (PMQ_TIMING_PARAM)&MQTimingParam[i] );
	}
	return (NULL);		//not found
}

// Return PLL register setting value
//
void GetMQPLL(float fFreq, unsigned long *ulPLLData)
{
	unsigned int i;

	*ulPLLData = 0UL;
	for ( i = 0; i < MAX_MQPLL; i++ )
		if ( fFreq == MQPLLParam[i].fFreq )
		{
			*ulPLLData = MQPLLParam[i].ulPLLData;
			break;
		}
}

// Program DAC for 8BPP mode
//
void SetupDAC(void)
{
	int i;
	
	// Enable Int mask for GC1 VDE Falling Edge - required only for 2 GCs
	// are on (accessed during blank time)
	//
	intREG(INT_MASK_REG,UM_GC1_VDE_F);

	
	InVBlank();

	for(i=0; i<16; i++)
	{
		palREG(i, PalDAC[i]);
	}

	// Reset Int mask for GC1 VDE Falling Edge
	//
	intREG(INT_MASK_REG,0);
}

#pragma optimize ("",off) // This is required to not let compiler mess up!
#ifdef CHECK_GE_NOTBUSY
void WaitGENotBusy()
{
	while( 1 )
	{
		if ( !(cpuREAD(DRAW_STATUS) & GE_BUSY) )
			return;
	}
}
#endif	//CHECK_GE_NOTBUSY

#ifdef CHECK_CMDFIFO
void WaitCmdFIFO( ULONG cnt )
{
	ULONG		ulStatus;
	
	while( 1 )
	{
		ulStatus = cpuREAD(DRAW_STATUS) & CMD_FIFO_MASK;
		if ( ulStatus >= cnt )
			return;
	}
}
#endif	//CHECK_CMDFIFO

#ifdef CHECK_SRCFIFO
void WaitSrcFIFO( ULONG cnt )
{
	ULONG		ulStatus;
	while( 1 )
	{
		ulStatus = cpuREAD(DRAW_STATUS) & SRC_FIFO_MASK;
		if ( (ulStatus >> 6) >= cnt )
			return;
	}
}
#endif	//CHECK_SRCFIFO

int InVBlank()
{
	volatile PULONG ulIntStat;

	ulIntStat = (PULONG)(m_pMMIO+IN_BASE+INT_STATUS_REG);

	// Make sure int occurs first
	udelay(1);	
	
	while ( !(*ulIntStat & ST_GC1_VDE_F) )
		;
	// Reset GC1 VDE F status bit - write 1 to clear the status
	intREG(INT_STATUS_REG,ST_GC1_VDE_F);

	udelay(1);	

	// Wait for next VDE falling edge for DAC access
	while ( !(*ulIntStat & ST_GC1_VDE_F) );

	// Here MQ200 should be in V blank period ...
	return 1;
}
#pragma optimize ("",on)

#define LOOP_CNT	   10
#define DELTA	           80
// This rourine ping pong GE and GE2 for different BLT operations
//
void do_blt(void)
{
	unsigned long ulTemp;
	int	crtx,crty,lcdx,lcdy;
	int	qx,qy;
	int	sx,sy;
	int iterations;
	int deltax,deltay;
	
  	// For CRT (GE)
	geREG(BASE_ADDRESS,dspconfig.crtstartaddr);
	ulTemp = dspconfig.crtstride;
	switch (dspconfig.crtbpp)
	{
		case 8:
			ulTemp |= GE_8BPP;
			break;
		case 16:
			ulTemp |= GE_16BPP;
			break;
		case 32:
			ulTemp |= GE_32BPP;
			break;
	}
	geREG(DEST_STRIDE,ulTemp);
	crtx = dspconfig.crtx;
	crty = dspconfig.crty;
	rfill(0, 0, crtx, crty, 0, 0xF0); // clear screen

  	// For LCD (GE2)
	geREG(BASE_ADDRESS2,dspconfig.panelstartaddr);
	ulTemp = dspconfig.panelstride;
	switch (dspconfig.panelbpp)
	{
		case 8:
			ulTemp |= GE_8BPP;
			break;
		case 16:
			ulTemp |= GE_16BPP;
			break;
		case 32:
			ulTemp |= GE_32BPP;
			break;
	}
	geREG(DEST_STRIDE2,ulTemp);
	lcdx = m_pFPControl->usHoriSize;
	lcdy = m_pFPControl->usVertSize;
	rfill2(0, 0, lcdx, lcdy, 0xFFFF, 0xF0); // clear screen
	qx = lcdx / 4;
	qy = lcdy / 4;
	sx = (lcdx - qx) / 2;
	sy = (lcdy - qy) / 2;
	rfill2(sx, sy, qx, qy, 0xC9B5, 0xF0);

	// Prepare for the demo looping ...
	//
	iterations = LOOP_CNT;
	deltax = DELTA;
	deltay = DELTA;
	do {
		unsigned int x = Random() % crtx;
		unsigned int y = Random() % crty;
		unsigned int dx =  Random() % (crtx - x);
		unsigned int dy =  Random() % (crty - y);
		unsigned int c = Random() % 16;
		unsigned int rop = Random() % 16;

		// CRT
		if (dx && dy)
			rfill(x, y, dx, dy, c, 0xF0);

		// LCD
		switch (c % 4)
		{
			case 0:
				deltax = DELTA;
				deltay = DELTA;
				break;
			case 1:
				deltax = -DELTA;
				deltay = DELTA;
				break;
			case 2:
				deltax = DELTA;
				deltay = -DELTA;
				break;
			case 3:
				deltax = -DELTA;
				deltay = -DELTA;
				break;
		}
		dx = sx + deltax;
		dy = sy + deltay;
		s2s(sx,sy,dx,dy,qx,qy,(rop|rop<<4));
	} while(--iterations);


       

}

void gen_pattern(void)
{
	int i,j, off=0;	
	unsigned short *fb=(short *)m_pFB;	
	for( j=0; j < 600; j++ )
	{		
		for( i=0; i < 800; i++ )
		{
			*fb++ = (i+off)&0xffff;
		}
		off+= ((1<<6)|(1<<11));		
	}	
}

short set_pixel( int x, int y, int color)
{	
	unsigned short old, *fb=(short *)m_pFB;	
	fb = fb + x + (y * 800);
	old=*fb;
	*fb=color;
	return(old);
}


void h_line( int x, int y, int dx, int color)
{
	int i;
	for( i=x; i < x+dx; i++ ) 
		set_pixel(i,y,color);
}

void v_line( int x, int y, int dy, int color)
{
	int i;
	for( i=y; i < y+dy; i++ ) 
		set_pixel(x,i,color);
}

void gen_lines(void)
{
	int i;
	
	for( i=0; i < 600; i+=20 )
		h_line( 0, i, 799, 0xffff);
	
	for( i=0; i < 800; i+=20 )
		v_line( i, 0, 599, 0xffff);
}

// Rectangle fill using GE2
//
void rfill2(unsigned long x, unsigned long y,
unsigned long dx, unsigned long dy, unsigned long colour, unsigned long rop)
{
	geWAITCMDFIFO(4);
	geREG(WIDTH_HEIGHT2, dx | (dy << 16));
	geREG(DEST_XY2, x | (y << 16));
	geREG(PAT_FG_COLOR2, colour);
	geREG(DRAW_CMD2,(MONO_PATTERN|MONO_SOLID|DO_BITBLT|rop));
}

// Screen to screen BLT using GE2
//
void s2s(unsigned int sx,
			unsigned int sy,
			unsigned int dx,
			unsigned int dy,
			unsigned int w,
			unsigned int h,
			unsigned int rop)
{
	unsigned long ulCmd;

	ulCmd = DO_BITBLT | rop;
	if (sx > dx)
	{
		sx += (w - 1);
		dx += (w - 1);
		ulCmd |= X_DIR;	// decrement on X
	}

	if (sy > dy)
	{
		sy += (h - 1);
		dy += (h - 1);
		ulCmd |= Y_DIR;	// decrement on Y
	}
	geWAITCMDFIFO(4);
	geREG(WIDTH_HEIGHT2, w | (h << 16));
	geREG(SRC_XY2, sx | (sy << 16));
	geREG(DEST_XY2, dx | (dy << 16));
	geREG(DRAW_CMD2,ulCmd);
}

// Rectangle fill using GE
//
void rfill(unsigned long x, unsigned long y,
unsigned long dx, unsigned long dy, unsigned long colour, unsigned long rop)
{
	geWAITCMDFIFO(4);
	geREG(WIDTH_HEIGHT, dx | (dy << 16));
	geREG(DEST_XY, x | (y << 16));
	geREG(PAT_FG_COLOR, colour);
	geREG(DRAW_CMD,(MONO_PATTERN|MONO_SOLID|DO_BITBLT|rop));
}
#if MAP_DEVICE 
void CleanUp(void)
{
	VirtualFree( m_pFB, 0, MEM_RELEASE );
	m_pFB = NULL;
	VirtualFree( m_pMMIO, 0, MEM_RELEASE );
	m_pMMIO = NULL;
}
#endif

#define BRIGHTNESS_STEPS	7
#define MAX_BRIGHT_REG		0x000000fc
#define _pwmRegisters           (unsigned long *)0x4be0e03c

void writeBrightness(int brightness)
{
	unsigned long dutyCycle;

	// Determine dutyCycle. 
	//Note: the lower the value, the brighter the display!

	dutyCycle = MAX_BRIGHT_REG - brightness;

        // Configure PWM0 (source clock = oscillator clock, pwm always enabled, 
        // zero, clock pre-divider = 4) pwm frequency = 12.0kHz
        
	*_pwmRegisters = 0x00000044 | (*_pwmRegisters & 0xffffff00);

	// Write to pwm duty cycle register.
	*_pwmRegisters =  ((dutyCycle << 8) & 0x0000ff00) | (*_pwmRegisters & 0xffff00ff);
}

void test_brightness(void)
{
	int i,j=10;
	while( j-- )
		for( i=0; i < 0xfc; i++ )
		{
			writeBrightness(i);
			udelay(10000);
		}
	
}


void test_mq200(void)
{
	while( ! serstat() )
	{
		gen_pattern();		
	}
	serin();
	while( ! serstat() )
	{
		do_blt();		
	}
	
	
}

//
// THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
// ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
// PARTICULAR PURPOSE.
//
// Copyright (c) 1999 MediaQ, Inc.
//

//------------------------------------------------------------------------
//Data Structure for MQ200 initialization
//------------------------------------------------------------------------
typedef struct DisplayConfig
{
	int			paneltype;			// Panel type
	int			panelbpp;			// Color depth
	int			panelstride;		// Stride for panel
	int			panelstartaddr;	// Start address for LCD panel
	int			crtx;					// X resolution for CRT
	int			crty;					// Y resolution for CRT
	int			crtbpp;				// CRT color depth
	int			crtfreq;				// CRT V frequency
	int			crtstride;			// Stride for CRT
	int			crtstartaddr;		// Start address for CRT

} DISPLAY_CONFIG, *PDISPLAY_CONFIG;

typedef struct MQInitParam
{
	ULONG       ulDC0;
	
	ULONG       ulMIU2;
	ULONG       ulMIU3;
	ULONG       ulMIU5;
	ULONG       ulMIU4;
	
	ULONG       ulD1;
	ULONG       ulD2;
	ULONG       ulGPO;
	ULONG       ulGPIO;

	ULONG       ulBaseAddr;
} MQ_INIT_PARAM, *PMQ_INIT_PARAM;

//Data Structure for timing parameter of each resolution
//
typedef struct MQTimingParam
{
	USHORT		usResoX;				//X resolution
	USHORT		usResoY;				//Y resolution
	USHORT		usFreq;					//Frequency
	ULONG       ulHD;                  	//Horz display 1 control
	ULONG       ulVD;                  	//Vert display 1 control
	ULONG       ulHS;                  	//Horz sync 1 control
	ULONG       ulVS;                  	//Vert sync 1 control
	ULONG       ulCRTC;						// GC01R - CRT Control
	float       fPLLFreq;  	            //Clock Frequency
} MQ_TIMING_PARAM, *PMQ_TIMING_PARAM;

//Data Structure for PLL data
//
typedef struct PLLParam
{
	float		fFreq;					//Clock Frequency
	ULONG		ulPLLData;				//PLLx control
} MQ_PLL_PARAM, *PMQ_PLL_PARAM;

//Data structure for flat panel interface
//
#define FRC_PATTERN_CNT			32
#define FRC_WEIGHT_CNT			8
typedef struct FRCControl
{
	ULONG		ulFRCPattern[FRC_PATTERN_CNT];	//FRC pattern control
	ULONG		ulFRCWeight[FRC_WEIGHT_CNT];	//FRC weight control

} FRC_CONTROL_STRUC, *PFRC_CONTROL_STRUC;

typedef struct FPControl
{
	USHORT		usHoriSize;		//Flat panel hori size
	USHORT	    	usVertSize;		//Flat panel vert size
	ULONG       	ulHD;                  	//Horz display control
	ULONG       	ulVD;                  	//Vert display control
	ULONG       	ulHS;                  	//Horz sync control
	ULONG       	ulVS;                  	//Vert sync control
	ULONG       	ulCRTC;			//GC01R - CRT Control
	float		fPLLFreq;		//PLLx Frequency
	ULONG		ulFPControl;		//Flat panel control
	ULONG		ulFPPinControl;		//Flat panel pin control
	ULONG		ulSTNControl;		//STN panel control
	ULONG		ulPWMControl;		//Contrast control
} FP_CONTROL_STRUC, *PFP_CONTROL_STRUC;

//-----------------------------------------------------------------------
// Mode Data
//-----------------------------------------------------------------------

// PLL1 frequency and corresponding P/M/N parameters for DC00R register
// - make sure it's NOT above 95MHz
MQ_PLL_PARAM MQPLLParam[] = 
{
	{  18.881F,	0x00ab0640 },
	{  25.175F,	0x00a30930 },
	{  31.500F,	0x00f50b30 },
	{  36.000F,	0x00d20830 },
	{  40.000F,	0x00e90830 },
	{  49.500F,	0x00900820 },
	{  50.000F,	0x00b20a20 },
	{  56.250F,	0x00b60920 },
	{  65.000F,	0x00fd0b20 },
	{  75.000F,	0x00f30920 },
	{  78.750F,	0x00cc0720 },
	{  83.000F,	0x00f20820 },
	{  94.500F,	0x007a0710 }
};       
#define MAX_MQPLL	(sizeof(MQPLLParam) / sizeof(MQPLLParam[0]))

// Palette data
ULONG PalDAC[16] =
{										
    0x00000000,
    0x00000080,   
    0x00008000,  
    0x00008080, 
    0x00800000,
    0x00800080,
    0x00808000, 
    0x00808080, 
    0x00C0C0C0,
    0x000000FF,
    0x0000FF00,
    0x0000FFFF,
    0x00FF0000,
    0x00FF00FF,
    0x00FFFF00,
    0x00FFFFFF
};
// Init Parameters ....
//
MQ_INIT_PARAM MQInitParam =
{
	0x0ef2082a,
	//0x0143E086,
	0x0043E086,
	0x6D6AABFF,
	0x0000010d,
	0x00000001,

	0x05000271,
	0x00000071,
	0x00000000,
	0x00000000,

	0x00000000
};

// LCD/CRT timing parameters for each resolution
//
MQ_TIMING_PARAM MQTimingParam[] = 
{
	{  //0 640 x 480 60Hz (25.175 MHz)
		640,480,60,							// X/Y/Freq
		(800-2) | (640L << 16),      	// HD Total + HD End
		(525-1) | ((480L-1) << 16),	// VD Total + VD End
		656 | (752L << 16),				// HS Start + HS End
		490 | (492L << 16),				// VS Start + VS End
		HSYNC_POLARITY_LOW|VSYNC_POLARITY_LOW|BLANK_PED_ENABLE,
		25.175F,						// PLLx frequency
	},

	{  //1 640 x 480 72Hz (31.5 MHz)
		640,480,72,							// X/Y/Freq
		(832-2) | (640L << 16),      	// HD Total + HD End
		(520-1) | ((480L-1) << 16),	// VD Total + VD End
		//664 | (704L << 16),				// HS Start + HS End
		688 | (728L << 16),				// HS Start + HS End
		489 | (492L << 16),				// VS Start + VS End
		HSYNC_POLARITY_LOW|VSYNC_POLARITY_LOW|BLANK_PED_ENABLE,
		31.5F,							// PLLx frequency
	},

	{  //2 640 x 480 75Hz (31.5 MHz)
		640,480,75,							// X/Y/Freq
		(840-2) | (640L << 16),      	// HD Total + HD End
		(500-1) | ((480L-1) << 16),	// VD Total + VD End
		//656 | (720L << 16),				// HS Start + HS End
		680 | (744L << 16),				// HS Start + HS End
		481 | (484L << 16),				// VS Start + VS End
		HSYNC_POLARITY_LOW|VSYNC_POLARITY_LOW|BLANK_PED_ENABLE,
		31.5F,							// PLLx frequency
	},

	{  //3 640 x 480 85Hz (36 MHz)
		640,480,85,							// X/Y/Freq
		(832-2) | (640L << 16),      	// HD Total + HD End
		(509-1) | ((480L-1) << 16),	// VD Total + VD End
		696 | (752L << 16),				// HS Start + HS End
		481 | (484L << 16),				// VS Start + VS End
		HSYNC_POLARITY_LOW|VSYNC_POLARITY_LOW|BLANK_PED_ENABLE,
		36.0F,							// PLLx frequency
	},

	{  //4 800 x 600 60Hz (40 MHz)
		800,600,60,							// X/Y/Freq
		(1054-2) | (800L << 16),		// HD Total + HD End
		(628-1) | ((600L-1) << 16),	// VD Total + VD End
		839 | (967L << 16),				// HS Start + HS End
		601 | (605L << 16),				// VS Start + VS End
		BLANK_PED_ENABLE,
		40.0F,							// PLLx frequency
	},
   
	{  //5 800 x 600 72Hz 50 MHz)
		800,600,72,							// X/Y/Freq
		(1040-2) | (800L << 16),		// HD Total + HD End
		(666-1) | ((600L-1) << 16),	// VD Total + VD End
		856 | (976L << 16),				// HS Start + HS End
		637 | (643L << 16),				// VS Start + VS End
		BLANK_PED_ENABLE,
		50.0F,							// PLLx frequency
	},
   
	{  //6 800 x 600 75Hz (49.5 MHz)
		800,600,75,							// X/Y/Freq
		(1056-2) | (800L << 16),		// HD Total + HD End
		(625-1) | ((600L-1) << 16),	// VD Total + VD End
		816 | (896L << 16),				// HS Start + HS End
		601 | (604L << 16),				// VS Start + VS End
		BLANK_PED_ENABLE,
		49.5F,							// PLLx frequency
	},
   
	{  //7 800 x 600 85Hz (56.25 MHz)
		800,600,85,							// X/Y/Freq
		(1047-2) | (800L << 16),		// HD Total + HD End
		(631-1) | ((600L-1) << 16),	// VD Total + VD End
		832 | (896L << 16),				// HS Start + HS End
		601 | (604L << 16),				// VS Start + VS End
		BLANK_PED_ENABLE,
		56.25F,							// PLLx frequency
	},
   
	{  //8 1024 x 768 60Hz (65 MHz)
		1024,768,60,						// X/Y/Freq
		(1344-2) | (1024L << 16),		// HD Total + HD End
		(806-1) | ((768L-1) << 16),	// VD Total + VD End
		1048 | (1184L << 16),			// HS Start + HS End
		771 | (777L << 16),				// VS Start + VS End
		HSYNC_POLARITY_LOW|VSYNC_POLARITY_LOW|BLANK_PED_ENABLE,
		65.0F,							// PLLx frequency
	},			

	{  //9 1024 x 768 70Hz (75 MHz)
		1024,768,70,						// X/Y/Freq
		(1327-2) | (1024L << 16),		// HD Total + HD End
		(806-1) | ((768L-1) << 16),	// VD Total + VD End
		1047 | (1183L << 16),			// HS Start + HS End
		771 | (777L << 16),				// VS Start + VS End
		HSYNC_POLARITY_LOW|VSYNC_POLARITY_LOW|BLANK_PED_ENABLE,
		75.0F,							// PLLx frequency
	},

	{  //10 1024 x 768 75Hz (78.750 MHz)
		1024,768,75,						// X/Y/Freq
		(1312-2) | (1024L << 16),		// HD Total + HD End
		(806-1) | ((768L-1) << 16),	// VD Total + VD End
		1040 | (1136L << 16),			// HS Start + HS End
		769 | (772L << 16),				// VS Start + VS End
		BLANK_PED_ENABLE,
		78.75F,							// PLLx frequency
	},

	{  //11 1024 x 768 85Hz (94.5 MHz)
		1024,768,85,						// X/Y/Freq
		(1375-2) | (1024L << 16),		// HD Total + HD End
		(808-1) | ((768L-1) << 16),	// VD Total + VD End
		1072 | (1168L << 16),			// HS Start + HS End
		769 | (772L << 16),				// VS Start + VS End
		BLANK_PED_ENABLE,
		94.5F,							// PLLx frequency
	}
};       
#define MAX_MQTIMING	(sizeof(MQTimingParam) / sizeof(MQTimingParam[0]))

//-----------------------------------------------------------------------
// Panel Data
//-----------------------------------------------------------------------

// Flat panel control register
//
FP_CONTROL_STRUC FPControlData[] =
{
	// Type 1 : SSTN VGA 8Bit Color - 72Hz
	// - Sanyo SSTN 640x480 8-bit color interface
	//
	{	// Flat panel control
		640,
		480,

		// Flat panel timing
		(832-2) | (640L << 16),			// HD Total + HD End
		(520-1) | ((480L-1) << 16),	// VD Total + VD End
		688 | (728L << 16),				// HS Start + HS End
		489 | (492L << 16),				// VS Start + VS End
		HSYNC_POLARITY_LOW|VSYNC_POLARITY_LOW|BLANK_PED_ENABLE,
		31.5F,							// PLLx frequency

		// Flat panel Control
		FP_TYPE_SSTN
		| FP_COLOR
		| SSTN_8BITS_MONOCLR
		| DITHER_PATTERN_3
		| DITHER_BASE_4BITS
		| FRC_16LEVEL
		| 0x00400000
		,

		// Flat panel pin control
		FSCLK_OUTPUT_ENABLE
		| SCLK_MASK
		//| FP_SCLK_16mA
		//| FP_FD0_16mA
		//| FP_DATA_16mA
		| FDE_ACTIVE_L	
		,

		// STN panel control
		0x00bd0000
		,
		0x5ca1
	},

	// Type 2 : DSTN 16 Bit VGA Color - 72Hz
	// - Hitachi 8.2" SX21V001
	// - Sanyo 10.4" LM-CJ53-22NTK
	// - Sharp 10.4" LM64C35P
	//
	{	// Flat panel control
		640,
		480,

		// Flat panel timing
		(832-2) | (640L << 16),			// HD Total + HD End
		(520-1) | ((480L-1) << 16),			// VD Total + VD End
		688 | (728L << 16),				// HS Start + HS End
		489 | (492L << 16),				// VS Start + VS End
		HSYNC_POLARITY_LOW|VSYNC_POLARITY_LOW|BLANK_PED_ENABLE,
		31.5F,							// PLLx frequency

		// Flat panel Control
		FP_TYPE_DSTN
		| FP_COLOR
		| DSTN_16BITS_MONOCLR
		| DITHER_PATTERN_3
		| DITHER_BASE_4BITS
		| FRC_16LEVEL
		| 0x0c840000
		,

		// Flat panel pin control
		FSCLK_OUTPUT_ENABLE
		| SCLK_MASK
		//| FP_SCLK_16mA
		//| FP_FD0_16mA
		//| FP_DATA_16mA
		| FDE_ACTIVE_L	
		,

		// STN panel control
		0x00bd0001
		,
		0x5ca1
	},

	// Type 3 : TFT 18 Bit VGA - 60Hz
	// - NEC 10.4" NL6448AC33-24
	//
	{	// Flat panel control
		640,
		480,

		// Flat panel timing
		(800-2) | (640L << 16),       	// HD Total + HD End
		(525-1) | ((480L-1) << 16),			// VD Total + VD End
		656 | (752L << 16),				// HS Start + HS End
		490 | (492L << 16),				// VS Start + VS End
		HSYNC_POLARITY_LOW|VSYNC_POLARITY_LOW|BLANK_PED_ENABLE,
		25.175F,						// PLLx frequency

		// Flat panel Control
		FP_TYPE_TFT
		| FP_COLOR
		| TFT_18BITS_COLOR
		| DITHER_PATTERN_3
		| DITHER_BASE_6BITS 
		,

		// Flat panel pin control
		FSCLK_OUTPUT_ENABLE
		,

		// STN panel control
		0x00bd0001
		,
		0x5ca1
	},

	// Type 4 : TFT 18 Bit SVGA - 60Hz
	// - Hitachi 12.1" 800x600 TX31D24VC1CAA
	//
	{	// Flat panel control
		800,
		600,

		// Flat panel timing
		(1054-2) | (800L << 16),		// HD Total + HD End
		(628-1) | ((600L-1) << 16),			// VD Total + VD End
		839 | (967L << 16),				// HS Start + HS End
		601 | (605L << 16),				// VS Start + VS End
		BLANK_PED_ENABLE,
		40.0F,							// PLLx frequency

		// Flat panel Control
		FP_TYPE_TFT
		| FP_COLOR
		| TFT_18BITS_COLOR
		| DITHER_PATTERN_3
		| DITHER_BASE_6BITS 
		,

		// Flat panel pin control
		FSCLK_OUTPUT_ENABLE
		//| FHSYNC_ACTIVE_L
		//| FVSYNC_ACTIVE_L
		//| FP_FSCLK_MAX
		//| FP_FD2_MAX
		//| FP_DATA_MAX
		,

		// STN panel control
		0x00bd0001
		,
		0x5ca1
	},

	// Type 5 : DSTN 16Bit SVGA Color Panel - 72Hz
	// - Hitachi 10.0" SX25S001
	// - Hitachi 12.1" SX25S003
	//
	{	// Flat panel control
		800,
		600,

		// Flat panel timing
		(1040-2) | (800L << 16),		// HD Total + HD End
		(666-1) | ((600L-1) << 16),			// VD Total + VD End
		856 | (976L << 16),				// HS Start + HS End
		637 | (643L << 16),				// VS Start + VS End
		BLANK_PED_ENABLE,
		50.0F,							// PLLx frequency

		// Flat panel Control
		FP_TYPE_DSTN
		| FP_COLOR
		| DSTN_16BITS_MONOCLR
		| DITHER_PATTERN_3
		| DITHER_BASE_4BITS
		| FRC_16LEVEL
		| 0x0c840000
		,

		// Flat panel pin control
		FSCLK_OUTPUT_ENABLE
		| SCLK_MASK
		//| FP_SCLK_16mA
		//| FP_FD0_16mA
		//| FP_DATA_16mA
		| FDE_ACTIVE_L	
		,

		// STN panel control
		0x00bd0001
		,
		0x5ca1
	},

	// Type 6 : DSTN 8 Bit VGA Color - 72Hz
	//
	{	// Flat panel control
		640,
		480,

		// Flat panel timing
		(832-2) | (640L << 16),       	// HD Total + HD End
		(520-1) | ((480L-1) << 16),			// VD Total + VD End
		688 | (728L << 16),				// HS Start + HS End
		489 | (492L << 16),				// VS Start + VS End
		HSYNC_POLARITY_LOW|VSYNC_POLARITY_LOW|BLANK_PED_ENABLE,
		31.5F,							// PLLx frequency

		// Flat panel Control
		FP_TYPE_DSTN
		| FP_COLOR
		| DSTN_8BITS_MONOCLR
		| DITHER_PATTERN_3
		| DITHER_BASE_4BITS
		| FRC_16LEVEL
		| 0x0c840000
		,

		// Flat panel pin control
		FSCLK_OUTPUT_ENABLE
		| SCLK_MASK
		//| FP_SCLK_16mA
		//| FP_FD0_16mA
		//| FP_DATA_16mA
		| FDE_ACTIVE_L	
		,

		// STN panel control
		0x00bd0001
		,
		0x5ca1
	},

	// Type 7 : SSTN VGA 16Bit Color - 72Hz
	//
	{	// Flat panel control
		640,
		480,

		// Flat panel timing
		(832-2) | (640L << 16),       	// HD Total + HD End
		(520-1) | ((480L-1) << 16),			// VD Total + VD End
		688 | (728L << 16),				// HS Start + HS End
		489 | (492L << 16),				// VS Start + VS End
		HSYNC_POLARITY_LOW|VSYNC_POLARITY_LOW|BLANK_PED_ENABLE,
		31.5F,							// PLLx frequency

		// Flat panel Control
		FP_TYPE_SSTN
		| FP_COLOR
		| SSTN_16BITS_MONOCLR
		| DITHER_PATTERN_3
		| DITHER_BASE_4BITS
		| FRC_16LEVEL
		| 0x00400000
		,

		// Flat panel pin control
		FSCLK_OUTPUT_ENABLE
		| SCLK_MASK
		//| FP_SCLK_16mA
		//| FP_FD0_16mA
		//| FP_DATA_16mA
		| FDE_ACTIVE_L	
		,

		// STN panel control
		0x00bd0000
		,
		0x5ca1
	},

	// Type 8 : SSTN VGA 8Bit Color - 60Hz
	// - Sanyo SSTN 640x480 8-bit color interface
	//
	{	// Flat panel control
		640,
		480,

		// Flat panel timing
		(800-2) | (640L << 16),       	// HD Total + HD End
		(525-1) | ((480L-1) << 16),			// VD Total + VD End
		656 | (752L << 16),				// HS Start + HS End
		490 | (492L << 16),				// VS Start + VS End
		HSYNC_POLARITY_LOW|VSYNC_POLARITY_LOW|BLANK_PED_ENABLE,
		25.175F,						// PLLx frequency

		// Flat panel Control
		FP_TYPE_SSTN
		| FP_COLOR
		| SSTN_8BITS_MONOCLR
		| DITHER_PATTERN_3
		| DITHER_BASE_4BITS
		| FRC_16LEVEL
		| 0x00400000
		,

		// Flat panel pin control
		FSCLK_OUTPUT_ENABLE
		| SCLK_MASK
		| FDE_ACTIVE_L	
		,

		// STN panel control
		0x00bd0000
		,
		0x5ca1
	},

	// Type 9 : DSTN 16 Bit VGA Color - 60Hz
	// - Hitachi 8.2" SX21V001
	// - Sanyo 10.4" LM-CJ53-22NTK
	// - Sharp 10.4" LM64C35P
	//
	{	// Flat panel control
		640,
		480,

		// Flat panel timing
		(800-2) | (640L << 16),       	// HD Total + HD End
		(525-1) | ((480L-1) << 16),			// VD Total + VD End
		656 | (752L << 16),				// HS Start + HS End
		490 | (492L << 16),				// VS Start + VS End
		HSYNC_POLARITY_LOW|VSYNC_POLARITY_LOW|BLANK_PED_ENABLE,
		25.175F,						// PLLx frequency

		// Flat panel Control
		FP_TYPE_DSTN
		| FP_COLOR
		| DSTN_16BITS_MONOCLR
		| DITHER_PATTERN_3
		| DITHER_BASE_4BITS
		| FRC_16LEVEL
		| 0x0c840000
		,

		// Flat panel pin control
		FSCLK_OUTPUT_ENABLE
		| SCLK_MASK
		| FDE_ACTIVE_L	
		,

		// STN panel control
		0x00bd0001
		,
		0x5ca1
	},

	// Type 10 : DSTN 16Bit SVGA Color Panel - 60Hz
	// - Hitachi 10.0" SX25S001
	// - Hitachi 12.1" SX25S003
	// - Sanyo LM-FC53-22NTK
	//
	{	// Flat panel control
		800,
		600,

		// Flat panel timing
		(1054-2) | (800L << 16),		// HD Total + HD End
		(628-1) | ((600L-1) << 16),			// VD Total + VD End
		839 | (967L << 16),				// HS Start + HS End
		601 | (605L << 16),				// VS Start + VS End
		BLANK_PED_ENABLE,
		40.0F,							// PLLx frequency

		0x0C1B4129
		,

		// Flat panel pin control
		FSCLK_OUTPUT_ENABLE
		| SCLK_MASK
		| FDE_ACTIVE_L	
		,

		// STN panel control
		0x00bd0001
		,
		//0x5ca1
		0x80100000
	},

	// Type 11 : DSTN 24Bit XGA Color Panel - 60Hz
	// - Hitachi 12.1" SX25S003
	//
	{	// Flat panel control
		1024,
		768,

		// Flat panel timing
		(1344-2) | (1024L << 16),		// HD Total + HD End
		(806-1) | ((768L-1) << 16),			// VD Total + VD End
		1048 | (1184L << 16),			// HS Start + HS End
		771 | (777L << 16),				// VS Start + VS End
		HSYNC_POLARITY_LOW|VSYNC_POLARITY_LOW|BLANK_PED_ENABLE,
		65.0F,							// PLLx frequency

		// Flat panel Control
		FP_TYPE_DSTN
		| FP_COLOR
		| DSTN_24BITS_COLOR
		| DITHER_PATTERN_3
		| DITHER_BASE_4BITS
		| FRC_16LEVEL
		| 0x0c840000
		,

		// Flat panel pin control
		FSCLK_OUTPUT_ENABLE
		| SCLK_MASK
		| FDE_ACTIVE_L	
		,

		// STN panel control
		0x00bd0001
		,
		0x5ca1
	},

	// Type 12 : DSTN 16Bit XGA Color Panel - 60Hz
	// - Hitachi 12.1" SX25S003
	//
	{	// Flat panel control
		1024,
		768,

		// Flat panel timing
		(1344-2) | (1024L << 16),		// HD Total + HD End
		(806-1) | ((768L-1) << 16),			// VD Total + VD End
		1048 | (1184L << 16),			// HS Start + HS End
		771 | (777L << 16),				// VS Start + VS End
		HSYNC_POLARITY_LOW|VSYNC_POLARITY_LOW|BLANK_PED_ENABLE,
		65.0F,							// PLLx frequency

		// Flat panel Control
		FP_TYPE_DSTN
		| FP_COLOR
		| DSTN_16BITS_MONOCLR
		| DITHER_PATTERN_3
		| DITHER_BASE_4BITS
		| FRC_16LEVEL
		| 0x0c840000
		,

		// Flat panel pin control
		FSCLK_OUTPUT_ENABLE
		| SCLK_MASK
		| FDE_ACTIVE_L	
		,

		// STN panel control
		0x00bd0001
		,
		0x5ca1
	},

	// Type 13 : TFT 18Bit XGA - 60Hz
	// - Hitachi 12.1" 800x600 TX31D24VC1CAA
	//
	{	// Flat panel control
		1024,
		768,

		// Flat panel timing
		(1344-2) | (1024L << 16),		// HD Total + HD End
		(806-1) | ((768L-1) << 16),			// VD Total + VD End
		1048 | (1184L << 16),			// HS Start + HS End
		771 | (777L << 16),				// VS Start + VS End
		HSYNC_POLARITY_LOW|VSYNC_POLARITY_LOW|BLANK_PED_ENABLE,
		65.0F,							// PLLx frequency

		// Flat panel Control
		FP_TYPE_TFT
		| FP_COLOR
		| TFT_18BITS_COLOR
		| DITHER_PATTERN_3
		| DITHER_BASE_6BITS 
		,

		// Flat panel pin control
		FSCLK_OUTPUT_ENABLE
		| FHSYNC_ACTIVE_L
		| FVSYNC_ACTIVE_L
		//| FP_SCLK_16mA
		//| FP_DATA_16mA 
		,

		// STN panel control
		0x00bd0001
		,
		0x5ca1
	},

	// Type 14 : TFT 24Bit XGA - 60Hz
	// - Hitachi 12.1" 800x600 TX31D24VC1CAA
	//
	{	// Flat panel control
		1024,
		768,

		// Flat panel timing
		(1344-2) | (1024L << 16),		// HD Total + HD End
		(806-1) | ((768L-1) << 16),			// VD Total + VD End
		1048 | (1184L << 16),			// HS Start + HS End
		771 | (777L << 16),				// VS Start + VS End
		HSYNC_POLARITY_LOW|VSYNC_POLARITY_LOW|BLANK_PED_ENABLE,
		65.0F,							// PLLx frequency

		// Flat panel Control
		FP_TYPE_TFT
		| FP_COLOR
		| TFT_24BITS_COLOR
		| DITHER_PATTERN_3
		| DITHER_BASE_6BITS 
		,

		// Flat panel pin control
		FSCLK_OUTPUT_ENABLE
		| FHSYNC_ACTIVE_L
		| FVSYNC_ACTIVE_L
		//| FP_SCLK_16mA
		//| FP_DATA_16mA 
		,

		// STN panel control
		0x00bd0001
		,
		0x5ca1
	},
	
	// Type 15 : TFT 18 Bit SVGA - 60Hz (Similar to type 4)
	// - NEC 12.1" 800x600 TX31D24VC1CAA
	//
	{	// Flat panel control
		800,
		600,

		// Flat panel timing
		(1054-2) | (800L << 16),		// HD Total + HD End
		(628-1) | ((600L-1) << 16),			// VD Total + VD End
		839 | (967L << 16),				// HS Start + HS End
		601 | (605L << 16),				// VS Start + VS End
		BLANK_PED_ENABLE,
		40.0F,							// PLLx frequency

		// Flat panel Control
		FP_TYPE_TFT
		| FP_COLOR
		| TFT_18BITS_COLOR
		| DITHER_PATTERN_3
		| DITHER_BASE_6BITS 
		,

		// Flat panel pin control
		0x03000020
		//FSCLK_OUTPUT_ENABLE
		//| FHSYNC_ACTIVE_L
		//| FVSYNC_ACTIVE_L
		//| FP_FSCLK_MAX
		//| FP_FD2_MAX
		//| FP_DATA_MAX
		,

		// STN panel control
		0x00bd0001
		,
		0x5ca1
	},
	
	// Type 16 : SSTN VGA 8Bit Color - 90Hz
	// - Sharp LM8M64 SSTN 640x240 8-bit color interface
	//
	{	// Flat panel control
		640,
		240,

		// Flat panel timing
		(793-2) | (640L << 16),			// HD Total + HD End
		(262-1) | ((240L-1) << 16),		// VD Total + VD End
		647 | (704L << 16),				// HS Start + HS End
		245 | (246L << 16),				// VS Start + VS End
		HSYNC_POLARITY_LOW|VSYNC_POLARITY_LOW|BLANK_PED_ENABLE,
		25.175F,							// PLLx frequency

		// Flat panel Control
		FP_TYPE_SSTN
		| FP_COLOR
		| SSTN_8BITS_MONOCLR
		| DITHER_PATTERN_1
		| DITHER_BASE_4BITS
		| FRC_16LEVEL
		| 0x00400000
		,

		// Flat panel pin control
		FSCLK_OUTPUT_ENABLE
		| SCLK_MASK
		//| FP_SCLK_16mA
		//| FP_FD0_16mA
		//| FP_DATA_16mA
		| FDE_ACTIVE_L	
		,

		// STN panel control
		0x00bd0000
		,
		0x5ca1
	}
};

// Flat panel FRC weight/pattern registers
//
FRC_CONTROL_STRUC FRCControlData =
{

		0x97A4C5F8, 0x61E3DB02,
		0x3D0E6F52, 0xCB4971A8,
		0x794A2B16, 0x8F0D35EC,
		0xD3E081BC, 0x25A79F46,
		0x1F2C4D70, 0xE96B538A,
		0xB586E7DA, 0x43C1F920,
		0xF1C2A39E, 0x0785BD64,
		0x5B680934, 0xAD2F17CE,
		0x794A2B16, 0x8F0D35EC,
		0xD3E081BC, 0x25A79F46,
		0x97A4C5F8, 0x61E3DB02,
		0x3D0E6F52, 0xCB4971A8,
		0xF1C2A39E, 0x0785BD64,
		0x5B680934, 0xAD2F17CE,
		0x1F2C4D70, 0xE96B538A,
		0xB586E7DA, 0x43C1F920,
		0x80800000, 0x88888420,
		0x94a49248, 0xaaaaaa54,
		0x6b5b55ab, 0x77776db7,
		0x7f7f7bdf, 0xffff7fff
};

int printf(const char *fmt,...);
void udelay(long usec);
void InitIo(void);
void set_led(int onoff );
int pr_chk_sum(void);
int cache_off(void);
void cache_on(void);
void cache_flush(void);
void cache_restore(int);
void hardware_poll(void);
int pcmcia_id(void);
void InitSerial(void);
int serout(int);
int serin(void);
int serstat(void);
int debounce(int status);
void setup_memory_timing(void);
int restore_timing(int newspeed);
int setup_write_timing(void);
extern char * set_progress(int cur,int len);
int set_image_length(int len);
int puts( const char *s);
int display_on(int);
int setup_color(void);
int cmp_mem(long *s1, long *s2, int size, int flag );
long cmp_flash(long *s1, long *s2, int size );
long gtext_sum(void);
long get_stackptr(void);
long stack_used( void);
void print_stack(void);
void enable_irq(int no);
void disable_irq(int no);
int test_mem(unsigned long start, unsigned long end, int print);
typedef void (*Function)(void);
unsigned  exceptionHandler(int v,Function fkt);
extern void catch_irq(void);
void trash_cache(void);
int erase_memory(void);
int get_processor_id(void);
unsigned long gen_checksum(unsigned  long start,unsigned  long cnt);
int check_boot_memory(void);



#define UCH
typedef unsigned char  uch;
typedef unsigned short ush;
typedef unsigned long  ulg;
ulg decompress_image(ulg output_start, ulg free_mem_ptr_p, ulg free_mem_ptr_end_p, 
		     char *data_start, int data_size);

int gethex(int (*inp)(void), int (*outp)(int) );
int get_string(char *dst,int (*eof)(int),int maxcnt,int (*inp)(void),int (*outp)(int));
int memdump( void *adr, int cnt );
int memdumpw( void *adr, int cnt );
int memdumpl( void *adr, int cnt );
void serial_get_file(void);
int  test_serial_download(void);
void fast_cpy_wrds(long *, long *,long);
void test_codec_gpios(void);

extern int serial_download_available;
extern int  download_started;

extern void test_smc(void);
void create_flashimage(unsigned long magic);
void burst_test(void);
void power_off(void);
void soft_reset(void);