MilCAN processors

Hi Everyone,

One of the MilCAN specifications is that a node is not allowed to issue an
error frame to get a message retransmitted. As I understand it the
designers of MilCAN wanted to insure that the Sync Flag Message always
showed up at exactly the same time.  Since the number of replies in each
sync slot are restricted only a large burst of higher priority messages
could thwart the sync flag.  And an error burst that caused retries.

For example.  Imagine there is time for 20 messages between SYNC FLAGs.
The system designer has one SYNC FLAG where there are 18 replies leaving
room for two ASYNC messages.  Say 4 of the replies are corrupted by a
noise burst during the CRC.  The retries would now extend past the time
point for a new SYNC FLAG and potentially it would be shifted or delayed.
Plus old data would show up in the next SYNC Slot.

The trouble is,  there are very few CAN devices out there that can have
the ERROR frame turned off.  Yes, the node can go to listen mode but then
all messages get through including ones with invalid CRCs.

Has anyone run into a processor family where this is possible?  Am I
misinterpreting the MilCAN spec?

Best Regards,

John Dammeyer


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