RE: MilCAN processors

Hi John, Wim,

In my opinion error frames should be produced also in MILCAN, because 
everyone has to know that the message is invalid. The CAN-controllers 
should have the possibility to do a so-called "single-shot" 
transmission. The good-old SJA1000 controller can do that and I think 
also more modern CAN controllers. If you set TX request and Tx abort 
simultaniously a single-shot transmission is performed.

Kees

Stremerch, Wim schreef op 20.12.2012 07:51:
> Message
>
> Hi John,
>
> Error frames are allowed on the bus, but if a controller sees an 
> error
> frame it should not retransmit the message.
>
> We use a controller that supports TTCAN. In this mode it will not
> retransmit the message when an error frame is received.
>
> Best regards,
>
> Wim Stremerch
>
> FROM: [email protected]
> [mailto:[email protected]] ON BEHALF OF 
> John
> Dammeyer
> SENT: donderdag 20 december 2012 1:08
> TO: 'CANLIST'
> SUBJECT: [CANLIST] MilCAN processors
>
> Hi Everyone,
>
> One of the MilCAN specifications is that a node is not allowed to
> issue an error frame to get a message retransmitted. As I understand
> it the designers of MilCAN wanted to insure that the Sync Flag 
> Message
> always showed up at exactly the same time. Since the number of 
> replies
> in each sync slot are restricted only a large burst of higher 
> priority
> messages could thwart the sync flag. And an error burst that caused
> retries.
>
> For example. Imagine there is time for 20 messages between SYNC 
> FLAGs.
> The system designer has one SYNC FLAG where there are 18 replies
> leaving room for two ASYNC messages. Say 4 of the replies are
> corrupted by a noise burst during the CRC. The retries would now
> extend past the time point for a new SYNC FLAG and potentially it
> would be shifted or delayed. Plus old data would show up in the next
> SYNC Slot.
>
> The trouble is, there are very few CAN devices out there that can 
> have
> the ERROR frame turned off. Yes, the node can go to listen mode but
> then all messages get through including ones with invalid CRCs.
>
> Has anyone run into a processor family where this is possible? Am I
> misinterpreting the MilCAN spec?
>
> Best Regards,
>
> John Dammeyer
>
> "ELS! The Solution"
> Automation Artisans Inc.
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