RE: How slow is too slow and timing settings

You're not the first to think you are running a different bit rate from what
you really are.  It's one of the reasons I always suggest buying a small CAN
dongle for initial debugging or as I said in a different reply, use the
scope to verify the bit times.  I had to go back to an older WIN-XP system
to find this application that I have used to set up bit times which is
specific to the MCP2515.

http://www.intrepidcs.com/support/mbtime.htm

Unless you expect your oscillators to vary widely an SJW of 1 is all you
need.  I ran the MCP2515 at 20kbps but with a 16Mhz crystal.  The problem
you may run into is the addition of other hardware that isn't based on the
ATMEL clock.  It's one of the reasons to use a standard clock frequency for
the CAN part and fudge the UART.  Remember the 1.8432MHz crystals are
designed for best UART frequencies to generate the odd numbers like 57600 or
9600 baud.  That frequency doesn't work well for exactly 50kbps.  Better off
to run your processors at 16MHz and tolerate a few percent on the UART and
have the CAN bus perfect.

John Dammeyer


> -----Original Message-----
> From: [email protected] [mailto:canlist-
> [email protected]] On Behalf Of Chuck Hackett
> Sent: September-13-14 4:32 PM
> To: [email protected]
> Subject: [CANLIST] How slow is too slow and timing settings
> 
> I put a scope on the CAN bus on the bench today and discovered that, due
to
> a programming error in setting the clock, my CAN bus is running at about
10
> kbps rather than 125 kbps.  Can this cause problems?, i.e.: 'Too' slow?
> 
> I have been reading AN754 ("Understanding Microchip's CAN Module Bit
> Timing") and checking the timing settings I currently have in the code
which
> I had copied from some example code I found on the Internet some time
> ago
> when I first started with the MCP2515.
> 
> The settings are:
> 	BLTMODE = 1
> 	Sample = 1x
> 	SJW = 1 (0 coded in CFG1)
> 	PSEG = 3 (2 coded in CFG2)
> 	SEG1 = 8 (7 coded in CFG2)
> 	SEG2 = 8 (7 coded in CFG3)
> 
> 
> In light of comments here and my readings.  I'm thinking that I need to
> change things to:
> 
> Given:
>        Desired bus rate = 61.442kbps
>        Max bus length = 2,000 feet = ~610m
>        One-way propagation delay (only cable is significant in my case) =
> 5ns/m * 610 = 3us
>        MCP Clock = 1.8432 Mhz
> 
> 	Note: Due to the current PCB design I am restricted to:
> 
> 		MCP Clock = (14.7456Mhz CPU clock) / (2 * (1 + OCR2))
> 
> 	where OCR2 is a control value for Timer-Counter #2 of ATMega1284p
> processor)
> 
> Using AN754, a spreadsheet and this timing calculator:
> http://www.kvaser.com/support/calculators/bit-timing-calculator/
> 
> I come up with:
> 
> NBT = 16.2760 us
> TQ = 1.0851 us
> TQs per bit time = 15
> 
> PSEG = 5 (actually allows bus up to 1,085 meters)
> 
> 10 TQ left over for SEG1 & SEG2 allocated as:
> 
> PSEG1 = 6
> PSEG2 = 4
> 
> This results in a sample point of 77.5%
> 
> My understanding is that I can use an SJW of 4 which should allow for
> maximum clock tolerance.
> 
> Misc:
> 	BLTMODE = 1
> 	Sample = 1x
> 
> Should I consider 3-point sampling?
> 
> Cheers,
> 
> Chuck Hackett
> "Good judgment comes from experience, experience comes from bad
> judgment"
> 7.5" gauge Union Pacific Northern (4-8-4) 844
> http://www.whitetrout.net/Chuck
> 
> 
> 
> 
> 
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