Stuffing at end of CRC?

Hello Guys

I am running simulations to verify CAN RTL.
In one of the scenario, I encountered a case for which I am not sure of the
behavior from testbench and rtl.

Scenario is random data is generated such that last 5 bits of the CRC is
all recessive. So my testbench inserts next bit dominant.

Now from rtl side, it does not expect any stuffing as 15bits of CRC is over
and it sees CRCDelim as dominant and declare a form error.

The problem is I am not sure what should be the right behav? Looked at spec
also but no help.

Can anyone here help me get this through?

Dhaval

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