Re: Stuffing at end of CRC?

Thanks John.

Dhaval

On Mon, Sep 22, 2014 at 8:59 AM, John Dammeyer <[email protected]>
wrote:

> The CRC SEQUENCE  is encoded with BIT STUFFING.  If the CRC Sequence has
> 5 identical bits then it follows with a stuff bit.   It doesn’t matter
> which bits.
>
> Think of it this way.
>
> A transmitter state machine resets a counter every time the bit changes
> between dominant and recessive increments every time the bit is the same as
> the last one.  When it reaches 5 bits it inserts a stuff bit of the
> opposite polarity and resets the counter.
>
> A receiver state machine resets a counter every time the bit changes
> between dominant and recessive and increments every time the bit is the
> same as the last one.  When it reaches 5 bits it verifies that the next
> bit is the opposite polarity and removes it from the bit stream so it
> doesn’t end up in the message accumulation buffer.  The flag is cleared
> and the counter reset.
>
> Since the receiver stuff bit flag is set signaling that a stuff bit is
> expected, the CRC SEQUENCE isn’t  complete until the flag is reset.
>
> John Dammeyer
>
>
>
> *From:* [email protected] [mailto:
> [email protected]] *On Behalf Of *Dhaval U Shah
> *Sent:* September-21-14 4:40 PM
> *To:* [email protected]
> *Subject:* [CANLIST] Stuffing at end of CRC?
>
>
>
> Hello Guys
>
> I am running simulations to verify CAN RTL.
> In one of the scenario, I encountered a case for which I am not sure of
> the behavior from testbench and rtl.
>
> Scenario is random data is generated such that last 5 bits of the CRC is
> all recessive. So my testbench inserts next bit dominant.
>
> Now from rtl side, it does not expect any stuffing as 15bits of CRC is
> over and it sees CRCDelim as dominant and declare a form error.
>
> The problem is I am not sure what should be the right behav? Looked at
> spec also but no help.
>
> Can anyone here help me get this through?
>
> Dhaval
>
> Sent from Samsung Galaxy GT-N7000
>