CAN bit timing synchronization question

Hi Everyone,

I was reading the dsPIC33FJ128MC802 microcontroller's ECAN manual, section
21.9.3.
http://ww1.microchip.com/downloads/en/DeviceDoc/70185C.pdf


I have a question about what was stated there:

" Two types of synchronization are used – Hard Synchronization and
Resynchronization. A Hard
Synchronization occurs once at the start of a frame. Resynchronization
occurs inside a frame.

• Hard synchronization takes place on the recessive-to-dominant transition
of the start bit.
The bit time is restarted from that edge.

• Resynchronization takes place when a bit edge does not occur within the
Synchronization
Segment in a message. One of the Phase Segments is shortened or lengthened
by an
amount that depends on the phase error in the signal. The maximum amount
that can be
used is determined by the Synchronization Jump Width parameter
(CiCFG1<SJW>). "

So I think I understand the first point, which means that the start of
frame bit has to start with a recessive to dominant transition, and that is
a reference point for the receiver to start counting the bit times.

I have trouble with the second point. Why would there be a bit edge when
for example I am transmitting two ones after each other? So how does it
know that there was supposed to be a bit edge there? Or is this why the
protocoll stuffs an extra different bit when there are too many same
consecutive bits on the line?

Any help is appreciated,
Fekete Tamás (Tamás=Thomas in english)




-- 
"there is no spoon"