RE: RE: [OpenGarages] Will Superposition of error flags desynchronize a active-transmitter passive-receiver bus??

Remember when you have only two nodes on the bus that the failure of =
Node 2 into error passive means that Node 1 will not be alerted to =
errors detected by Node 2.  The lack of the ACK is the only means that =
Node 1 will detect a problem and will then retransmit.

The lack of the ACK creates a properly formed error flag with =
intermission and bus idle before a re-transmission which will =
resynchronize Node2.

But really, your CAN bus should have CAN_HI, CAN_LOW and CAN_GND and be =
a shielded properly terminated transmission line with adequate distance =
between nodes and stubs that aren't too long.  Under those conditions =
the likelihood of the error you describe is virtually impossible anyway.

John Dammeyer

> -----Original Message-----
> From: [email protected] [mailto:[email protected]] On
> Behalf Of Christiano SA
> Sent: August-21-18 11:00 AM
> To: [email protected]
> Subject: Re: RE: [CANLIST] [OpenGarages] Will Superposition of error =
flags
> desynchronize a active-transmitter passive-receiver bus??
>=20
> > *** No I don't think so.  Node 2 detects Stuff Error at this point, =
not an
> error flag, so Node 2 will start a Passive Error Flag expecting =
dominant bits
> but read recessive bits.  Until it sees a properly formed error flag =
or bus idle,
> Node 2 will not receive any messages.  It's likely the 8 recessive =
bits and the
> 3 intermission bits (11 bits) will reset the Node2 state machine since =
it's
> error passive.  It will therefore correctly detect the next message.
> >
>=20
> Ok, correcting:
>=20
> Node2 will interpret the same signal as follow:
> ______-----------
> =3D
> ___ =3D> Normal dominant 3 bits (it doesn't know that an error =
happened in
> the Node1 ) +
> *** Error detected!! Wrong Stuffing. (Suppose there was others =
dominant
> bits before)
> ___ =3D> Trying to get 6 equal, failed with 3 dominant
> ------ =3D> Trying again: OK! 6 equal recessive bits, the passive =
error flag is
> complete! (as the ISO says) +
> ----- =3D> error delimiter ( it has 8 recessive bits but the signal =
presents only 5
> of them)
>=20
> > *** So you are saying that the bus is noisy and Node 2 only sees 5
> recessive bits before a dominant appears?
>=20
> No, I just was saying that the same 17 bits would be interpreted =
differently
> by two nodes; while Node1 might see a SOF, Node2 is yet inside the =
error
> delimiter. I will try draw it below:
>=20
> 0123456789abcdefg
> ______-----------
>=20
> Node 1:
> [0,5] =3D error flag
> [6,d] =3D error delimiter
> [e,g] =3D intermission
>=20
> Node 2:
> [0,2] =3D normal operation (data frame)
> Error happens because stuffing
> [3,5] =3D error flag field (trying to get 6 equal bits, but fail)
> [6,b] =3D error flag field (trying to get 6 equal bits, success)
> [c,g] =3D error delimiter (show only 5 bits)
>=20
> > ***Are these questions for a school assignment?
>=20
> No.
>=20
>=20
> Now I will draw the same analysis using the interpretation which a =
Think is
> correct:
>=20
> 0123456789abcdefg
> ______-----------
>=20
> Node 1:
> [0,5] =3D error flag
> [6,d] =3D error delimiter
> [e,g] =3D intermission
>=20
> Node 2:
> [0,2] =3D normal operation (data frame)
> Error happens because stuffing
> [3,5] =3D error flag field (trying to get 6 equal bits, but counting =
the previous 3
> dominant bits, success, error flag is complete)
> [6,d] =3D error delimiter
> [e,g] =3D intermission
>=20
> Notice: The two nodes now are synchronized. I tried to get a "bug" =
using this
> approach but it works correctly always, therefore I think that it is =
the correct
> interpretation.
>=20
>=20
> > Sent: Tuesday, August 21, 2018 at 1:19 PM
> > From: "John Dammeyer" <[email protected]>
> > To: [email protected]
> > Subject: RE: [CANLIST] Re: [OpenGarages] Will Superposition of error =
flags
> desynchronize a active-transmitter passive-receiver bus??
> >
> > See below:
> >
> > > -----Original Message-----
> > > From: [email protected] [mailto:[email protected]]
> On
> > > Behalf Of Christiano SA
> > > Sent: August-21-18 6:25 AM
> > > To: [email protected]
> > > Cc: [email protected]; [email protected]
> > > Subject: [CANLIST] Re: [OpenGarages] Will Superposition of error =
flags
> > > desynchronize a active-transmitter passive-receiver bus??
> > >
> > > Conventions:
> > > _ =3D 0 =3D dominant bit
> > > - =3D 1 =3D recessive bit
> > >
> > > Imagine the signal:
> > > ______-----------
> > >
> > > That is, 6 dominant bits + 11 recessive bits.
> > >
> > > If my previous interpretation of ISO was correct (I think that it =
wasn't),
> so:
> > >
> >
> > *** Missing in this scenario is _why_ Node 1 is generating the Error =
Flag.
> Assuming a bit error? The previous bit was recessive when it should =
have
> been dominant?  Therefore  Node 1 will _generate_ what follows.
> >
> > > Node1 will interpret it as follow:
> > > ______-----------
> > > =3D
> > > error flag (6 dominant bits) +
> > > error delimiter (8 recessive bits) +
> > > intermission (3 recessive bits)
> > >
> > > Now Node1 thinks that bus is idle and if Node1 has information to
> transmit,
> > > it will send a SOF.
> >
> > ***  Correct.
> > >
> > > However,
> > > Node2 will interpret the same signal as follow:
> > > ______-----------
> > > =3D
> > > error flag (6 dominant bits) +
> >
> > *** No I don't think so.  Node 2 detects Stuff Error at this point, =
not an
> error flag, so Node 2 will start a Passive Error Flag expecting =
dominant bits
> but read recessive bits.  Until it sees a properly formed error flag =
or bus idle,
> Node 2 will not receive any messages.  It's likely the 8 recessive =
bits and the
> 3 intermission bits (11 bits) will reset the Node2 state machine since =
it's
> error passive.  It will therefore correctly detect the next message.
> >
> > > 6 equal recessive bits +
> > > error delimiter ( it has 8 recessive bits but the signal presents =
only 5 of
> > > them)
> >
> > *** So you are saying that the bus is noisy and Node 2 only sees 5
> recessive bits before a dominant appears? If Node hasn't seen the =
correct
> 'form' of the message it will once again send passive error flags.  =
Until
> Node1 one finishes and creates an bus idle condition Node 2 will not
> receive messages.
> >
> > *** However now you no longer have Node1 receiving an ACK and
> therefore it transmits an Error Flag after the ACK.  So your Node 2 =
will have
> another chance to synchronize to Node 1.
> >
> > ***Are these questions for a school assignment?
> >
> > John Dammeyer
> > >
> > > When Node1 thinks that it can send a SOF, Node2 thinks that it is =
inside
> the
> > > error delimiter.
> > >
> > > --
> > >
> > > The correct interpretation probably is to think the "6 subsequent =
bits", as
> > > the ISO says, may have its left edge before of the detection of =
error
> > > condition.
> > > Such interpretation works very well with all cases that I have =
tested.
> > >
> > > Following such interpretation and applying to previous example, =
when
> > > Node2 detect a error condition, it has only 3 bits additional in =
order to
> > > complete 6 subsequent equal bits and the two nodes would be
> > > synchronized.
> > >
> > >
> > > > Sent: Monday, August 20, 2018 at 4:55 PM
> > > > From: "Collin Kidder" <[email protected]>
> > > > To: [email protected]
> > > > Cc: [email protected]
> > > > Subject: Re: [OpenGarages] Will Superposition of error flags
> > > desynchronize a active-transmitter passive-receiver bus??
> > > >
> > > > I don't think it's a problem. The error delimiter is to be 8 =
bits and
> > > > the interframe space is 3 bits so it seems to me that there will =
be
> > > > 8+3 =3D 11 recessive bits minimum at the end of an error frame. =
That
> > > > ought to be plenty of bits to get everyone on the same page =
before
> > > > another frame tries to come through.
> > > > On Mon, Aug 20, 2018 at 3:02 PM Christiano SA
> <[email protected]>
> > > wrote:
> > > > >
> > > > > Imagine the following situation:
> > > > >
> > > > > You have a bus with two nodes:
> > > > > node 1 =3D transmitter, active-error-node
> > > > > node 2 =3D receiver, passive-error-node
> > > > >
> > > > > Now an error happens at node 1. As it is a active node, it =
will transmit
> 6
> > > dominant bits, but... lets suppose that the third bit generate an =
error in
> the
> > > node2.
> > > > >
> > > > > The ISO 11898-1:2015, in the page 35 says:
> > > > >
> > > > > """""""""""""""""""""""""""""""""""""""
> > > > > Passive error flags initiated by receivers shall not be able =
to prevail
> over
> > > any activity on the bus.
> > > > > Therefore, error-passive receivers shall always wait for 6 =
subsequent
> > > equal bits after detecting an error condition.
> > > > > The passive error flag is complete when these 6 equals bits =
have
> been
> > > detected.
> > > > > """""""""""""""""""""""""""""""""""""""
> > > > >
> > > > > So, from node2's view, it will have to wait 3 (6 total - past =
3) dominant
> > > bits + 6 recessive bits to follow the rule "6 equal subsequent =
bits". At the
> > > end, node2 can enter in the "error delimiter".
> > > > > However, from the node1's view, it is remaining only 3 bits to =
enter in
> > > the "error delimiter".
> > > > >
> > > > > Isn't it happening desynchrony here?
> > > > >
> > > > > This question is being sended to 2 mailing lists:
> > > > > Canlist
> > > > > Opengarage group
> > > > >
> > > > > --
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