Question about CAN Controller bit timing logic
"Liu, Jianye" <[email protected]> Mon, 10 Feb 2020 17:22:20 +0000
| Newsgroups | gmane.comp.hardware.bus.can |
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Dear Sir or Madam,
I am Rocky Leo. I happened to see the some CAN BUS
file in library and I have some questions about the hardware level of
CAN Controller Bit Timing Logic part.
I am interested in hardware part about CAN Controller Data
Synchronization, so could you tell me how does the Bit Time Logic
detect the phase difference and convert the phase difference into
exact number of TQs(Time Quanta) to help CAN controller synchronize
the Data?
Best Regard,
Rocky Leo
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<p class=3D"MsoNormal">Dear Sir or Madam,</p>
<p class=3D"MsoNormal"><o:p> </o:p></p>
<p class=3D"MsoNormal"><o:p> </o:p></p>
<p class=3D"MsoNormal">I am Rocky Leo. I happened to see the some CAN BUS <=
br>
file in library and I have some questions about the hardware level of=
<br>
CAN Controller Bit Timing Logic part.<o:p></o:p></p>
<p class=3D"MsoNormal"><br>
I am interested in hardware part about CAN Controller Data <o:p></o:p></p>
<p class=3D"MsoNormal"> Synchronization, so could you tell me how does=
the Bit Time Logic
<br>
detect the phase difference and convert the phase difference into <br>
exact number of TQs(Time Quanta) to help CAN controller synchronize <br>
the Data?<o:p></o:p></p>
<p class=3D"MsoNormal"><o:p> </o:p></p>
<p class=3D"MsoNormal">Best Regard,<o:p></o:p></p>
<p class=3D"MsoNormal"><o:p> </o:p></p>
<p class=3D"MsoNormal">Rocky Leo<br>
<br>
<o:p></o:p></p>
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