Re: STM32F1 - Sysclock
Uwe Bonnes <bon-1JbLm1bU5j5ZIx36JBfelj3+ndqKAYMe9FMPySWZwLkb1SvskN2V4Q@public.gmane.org>
| Newsgroups | gmane.comp.hardware.microcontrollers.ethernut |
|---|---|
| Message-ID | <[email protected]> |
>>>>> "Achim" == Achim <[email protected]> writes: Achim> Hi, i think in the current svn-version of stm32f1_clk.c is a Achim> mistake configuring the system clock. Achim> In earlier versions a "Multiplier" was calculated fort he Achim> PLL-settings in SetSysClock(). In the current version this part Achim> is missing! I´ve tried to copy the old code into this module - Achim> then everything works fine again! Please specify what old patch you copied where, e.g. by diffing (-uw) old an new stm32f1_clk. The old clock setting scheme got unmanagable with all the new devices and I am in the process of reworking it. I also have no STM32F1 project that I have to maintain, so STM32F1 gets less attention. Bye -- Uwe Bonnes bon-1JbLm1bU5j5ZIx36JBfelj3+ndqKAYMe9FMPySWZwLkb1SvskN2V4Q@public.gmane.org Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ---------- _______________________________________________ http://lists.egnite.de/mailman/listinfo/en-nut-discussion