Re: Problem with ETH PHY Lan8742
Uwe Bonnes <bon-1JbLm1bU5j5ZIx36JBfelj3+ndqKAYMe9FMPySWZwLkb1SvskN2V4Q@public.gmane.org> Fri, 2 Sep 2016 14:31:21 +0200
| Newsgroups | gmane.comp.hardware.microcontrollers.ethernut |
|---|---|
| Message-ID | <[email protected]> |
>>>>> "Ole" == Ole Reinhardt <ole.reinhardt-L1vi/[email protected]> writes: ... Ole> Not really. But I can imagine problems with the default Ole> configuration of the MII pins of the CPU during CPU reset. That's Ole> the reason for the above mentioned PHY reset code, that I added in Ole> my project. SVN Rev.6524 provides a way for LAN87xx chips to set the normally strap provides values by software. No GPIO pin and connection for a dedicated PHY reset is needed. Bye -- Uwe Bonnes bon-1JbLm1bU5j5ZIx36JBfelj3+ndqKAYMe9FMPySWZwLkb1SvskN2V4Q@public.gmane.org Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 1623569 ------- Fax. 06151 1623305 --------- _______________________________________________ http://lists.egnite.de/mailman/listinfo/en-nut-discussion