Re: CPLD and socket board pins mapping

Code example to toggle a pin on UIO.
http://lists.dalsemi.com/maillists/tini/2003-September/029081.html

XIO is only available with correct part, and not accounted for in Verilog
source.

I would confirm pin assignments for UIO in Xilinx software, from what I
recall it was not complete.  As any pin not specified will auto connect
itself, which may end up in some confusion.

----- Original Message -----
From: "Simon Wong" <swong-5bdsyQ5pCqFWk0Htik3J/[email protected]>
To: <tini-6tN4nzCoH/[email protected]>
Sent: Thursday, January 08, 2004 4:19 PM
Subject: [TINI]CPLD and socket board pins mapping


> Hi,
>
> I've mounted a CPLD and a regulator onto the 400 socket board. I'm able to
> load the sample CPLD bitmap from Maxim onto the CPLD.
>
> My question is, what are the pin mappings? There's UIO(x) and XIO(y), but
I
> don't know what they do. Are some of them data outputs from the DataPort
> class? Are some of them address lines from PCE or CE? I can't seem to find
> documentation on these IO ports.
>
> Thanks,
> Simon Wong
>
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