[Fwd: Re: Integrated dithered master oscillator]

A google search of ethernet + clock + dither yielded this article:

http://www.sigcon.com/Pubs%5Cedn%5Cclockmod.htm

It had these negative comments:

"... For example, you can never use a modulated clock as the 
reference-clock input to an advanced data-communication transceiver 
(Ethernet, Fibre Channel, FDDI, ATM, SONET, or ADSL). These parts 
require a pristine, jitter-free reference clock. When connected to a 
jittery clock, these transceivers may fail to lock, or lock poorly, 
leading to data errors or other flaky behavior. Never use an 
intentionally modulated clock as the reference input for any kind of 
data-communication transceiver."

But, things change, and dithered clocks are getting more popular,
and PLLs have improved, so....

Still, every PLL has its own frequency response characteristic in
its ability to follow changes in the reference clock. I would be
wary about this unless the PLL had been characterized with the
dithered input (presumably the manufacturer of the device containing
the PLL would publish this fact). And tested extensively over a wide
variety of process variations and environmental conditions.

- C

Chris Fox wrote:

>Interesting question! I am trying to get my hands on a +/- 2% and a +/-
>4% at 25 MHz to try it out!
>
>Ethernet has got to be tolerant of variations in clock, and the PLL for
>the clock extractor has to work pretty fast, so I have a feeling that it
>will work!
>
>I plan to try it as soon as I can get some parts.
>
>Chris
>
>
>  
>

-- 
Chuck Wright
http://chuck-wright.com


-- 
Chuck Wright
http://chuck-wright.com


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