RE: [Fwd: Re: Integrated dithered master oscillator]
"Chris Fox" <[email protected]>
| Newsgroups | gmane.comp.hardware.microcontrollers.tini |
|---|---|
| Message-ID | <[email protected]> |
The key is the rate of the dither (about 20Khz in this case) and the shape of the modulation curve (triangular). So long as the typical Ethernet PLL can track it, you're OK. The question is, what is typical? The DS1087 has control pins that can be used to switch the dither on and off. Perhaps it would be best to connect this pin to a port pin so that the dither can be controlled(?). Chris -----Original Message----- From: tini-admin-6tN4nzCoH/[email protected] [mailto:[email protected]] On Behalf Of Chuck Wright Sent: Wednesday, February 04, 2004 9:42 AM To: tini-6tN4nzCoH/[email protected] Subject: [Fwd: Re: [TINI]Integrated dithered master oscillator] A google search of ethernet + clock + dither yielded this article: http://www.sigcon.com/Pubs%5Cedn%5Cclockmod.htm It had these negative comments: "... For example, you can never use a modulated clock as the reference-clock input to an advanced data-communication transceiver (Ethernet, Fibre Channel, FDDI, ATM, SONET, or ADSL). These parts require a pristine, jitter-free reference clock. When connected to a jittery clock, these transceivers may fail to lock, or lock poorly, leading to data errors or other flaky behavior. Never use an intentionally modulated clock as the reference input for any kind of data-communication transceiver." But, things change, and dithered clocks are getting more popular, and PLLs have improved, so.... Still, every PLL has its own frequency response characteristic in its ability to follow changes in the reference clock. I would be wary about this unless the PLL had been characterized with the dithered input (presumably the manufacturer of the device containing the PLL would publish this fact). And tested extensively over a wide variety of process variations and environmental conditions. - C Chris Fox wrote: >Interesting question! I am trying to get my hands on a +/- 2% and a +/- >4% at 25 MHz to try it out! > >Ethernet has got to be tolerant of variations in clock, and the PLL for >the clock extractor has to work pretty fast, so I have a feeling that it >will work! > >I plan to try it as soon as I can get some parts. > >Chris > > > > -- Chuck Wright http://chuck-wright.com -- Chuck Wright http://chuck-wright.com _______________________________________________ TINI mailing list TINI-6tN4nzCoH/[email protected] To UNSUBSCRIBE, edit your profile, or see list archives: http://lists.dalsemi.com/mailman/listinfo/tini _______________________________________________ TINI mailing list TINI-6tN4nzCoH/[email protected] To UNSUBSCRIBE, edit your profile, or see list archives: http://lists.dalsemi.com/mailman/listinfo/tini