Installing ISR for Interrupt 5
Chris Musial <cmusial-cK+/[email protected]>
| Newsgroups | gmane.comp.hardware.microcontrollers.tini |
|---|---|
| Message-ID | <[email protected]> |
I'm trying to install a handler for Interrupt 5 and am ending up hanging my
machine when the interrupt gets generated. I'm also installing a handler for
Interrupt 1 and this 1 is working OK, so I'm pretty sure I have the overall flow
right. I think my problem is that Interrupt 5 is shared by the 1-wire master
bus and I can't find the documentation for turning off those interrupts. The
documentation says I need to use OWMAD and OWMDR to turn off the EOWMI bit, but
I can't find anywhere that tells me where that bit is, or if there's anything
else I need to do. I did infer that the control register is used to turn it
off, but there must be something else. Here's my interrupt installation code:
clr EIE.0 ; disable int 5 (and 2-4)
mov OWMAD,#5 ; Select 1-wire control register
mov OWMDR,#0 ; Set EOWMI to disable the OW interrupts
mov dps, #1
mov dptr, #cardClockInt ; address of ISR
mov dps, #0
mov a, #43h ; interrupt vectors for ints 2-5
lcall System_InstallInterrupt
jz enableInt5
setb EIE.0
mov a,#4 ; error code - unable to install interrupt
sjmp Install_Exit
enableInt5:
setb EIE.0
...
The routine to install the interrupt returns success (it would return 4 if this
installation failed). Right now, the ISR is empty - just an IRET instruction,
but the board hangs as soon as the interrupt is generated. As I said, my
handler for interrupt 1 is working, but (a) - interrupt 5 is shared with
interrupts 2-4, and (b) it is multiplexed with the 1-wire bus. Is there
anything else I need to do when installing int 5?
Thanks for any help...
Chris Musial
cmusial-cK+/[email protected]
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