Installing ISR for Interrupt 5

Thanks Bryan,

I checked that the code is clearing IE5 and it is.  I'm still getting interrupt
5 firing continuously.  I have found how to clear the EOWMI bit and am now doing
that.  However when our engineer put a scope on the line, he saw that the cpu
was trying to drive the pin low while the external device was driving it high,
and that may be causing the constant firing of the interrupt.  The documentation
says that the port can operate as either a general purpose i/o port or in an
alternate mode based on the 'associated port 1 latch bit'.  I can't find any
documentation on this latch bit - is there some sort of setup I need to do so
that port 1.7 (as well as 1.4 - 1.6) will be an input port driving the interrupt?

Following is a snippet of the code for installing the interrupt:

IE2
equ
EXIF.4
IE3
equ
EXIF.5
IE4
equ
EXIF.6
IE5
equ
EXIF.7

  clr	EA
  clr	IE2
  clr	IE3
  clr	IE4
  clr	IE5
  mov   OWMAD,#5		; Select 1-wire control register
  anl	OWMDR,#01111111B	; Set EOWMI to disable the OW interrupts
  mov	dps, #1
  mov	dptr, #extDeviceInt	; ISR address
  mov	dps, #0
  mov a, #43h
  lcall System_InstallInterrupt
  jz	enableInts
  setb	EX2_5
  setb	EA
  mov	a,#com_dalsemi_system_ExternalInterruptException
  sjmp	Install_Exit  

enableInts:
  setb	EX2_5
  setb	EA

   ...

            ---------------------------

And here is the entry and exit code for the ISR:

extDeviceInt:
  clr	EX2_5
  push	psw
  push	acc
  push	dps
  PUSH_DPTR1
  PUSH_DPTR2

  jb	IE2,handleInt2
  jb	IE3,handleInt3
  jb	IE4,handleInt4
  clr	IE5
  ljmp	countDone     ; ignor int5 for now

handleInt3:
  ljmp	doHandleInt3
handleInt4:
  ljmp	doHandleInt4

handleInt2:
  clr	IE2
    ...
  ljmp  countDone

doHandleInt3:
  clr   IE3
    ...
  ljmp  countDone

doHandleInt4:
  clr   IE4
    ...

countDone:
  POP_DPTR2
  POP_DPTR1
  pop	dps
  pop	acc
  pop	psw
  setb	EX2_5
  reti


Thanks,

Chris Musial
cmusial-cK+/[email protected]

---------------------------

Chris Musial wrote:
> I'm trying to install a handler for Interrupt 5 and am ending up hanging my
> machine when the interrupt gets generated.  I'm also installing a handler for
> Interrupt 1 and this 1 is working OK, so I'm pretty sure I have the overall flow
> right.  I think my problem is that Interrupt 5 is shared by the 1-wire master
> bus and I can't find the documentation for turning off those interrupts.  The
> documentation says I need to use OWMAD and OWMDR to turn off the EOWMI bit, but
> I can't find anywhere that tells me where that bit is, or if there's anything
> else I need to do.  I did infer that the control register is used to turn it
> off, but there must be something else.  Here's my interrupt installation code:


Look in the DS80C400 Datasheet.  The DS80C400 user guide does not have 
the complete info on the 1-Wire master.  EOWMI is defined as bit 7 of 
the control register.

> The routine to install the interrupt returns success (it would return 4 if this
> installation failed).  Right now, the ISR is empty - just an IRET instruction,
> but the board hangs as soon as the interrupt is generated.  As I said, my
> handler for interrupt 1 is working, but (a) - interrupt 5 is shared with
> interrupts 2-4, and (b) it is multiplexed with the 1-wire bus.  Is there
> anything else I need to do when installing int 5?

Make sure to clear EXIF.7 (IE5), the /INT5 flag bit, before you reti out 
of your ISR.  I think the interrupt is continuously firing.

BTW, the 1-Wire code in TINIOS does not use interrupts so your code is 
safe from 1-Wire interrupts.


-- 
--
Bryan Armstrong



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