RE: Parallel I/O

I may be off, but I don't think the OS uses the PCE's at all, I believe it
just uses the CEs, and typically only a couple of the lower ones for memory
and flash. The EMAC SOM100ES carrier maps it's CPLD into DS400 memory space
using a CE and it works great. I don't think the PCE's are used for anything
but GPIO, and I wouldn't recommend trying to use them as anything but that.
See the "Design Considerations for DS80C400-based TINI Systems" pdf for a
good description of the memory map.

NZG.

-----Original Message-----
From: tini-admin-6tN4nzCoH/[email protected] [mailto:[email protected]]On Behalf Of
Jonathan Sharret
Sent: Friday, March 26, 2004 12:34 PM
To: tini-6tN4nzCoH/[email protected]
Subject: [TINI]Parallel I/O


Hi,

I'm trying to work out how the DS80C400 on the TINIm400 handles Parallel
I/O.  I've read through Don's book on the topic, but there are many
differences between the 390 and the 400 and I'd like to know if anyone
can clarify some points for me.

We're trying to interface the DS80C400 to a TI DSP.  We're using PCE3 as
the chip enable and RD and WR as the read and write enable signals.  The
DSP is programmed by loading a set of 7 registers.  The registers are
addressed by A0, A1 and A2 and data is loaded through the 8 data lines.
Basically there is no way to load the DSP other than byte-banging these
7 registers since the DSP does not open up its internal memory directly.

>From what I've read on this message board and from the DS80C400 data
sheets and user guide the following seems to be true:

The 400 chip has 8 chip enables and 4 peripheral chip enables.  The chip
enables are capable of addressing up to 4 MB each to a total of 16MB.
The peripheral chip enables are capable of addressing up to 1 MB each.

The Program and Data memory spaces on the 400 can be combined into a
shared memory space.  When the memory spaces are combined, the program
memory space "takes over" the data memory space and any peripheral chip
enable is subsumed by the corresponding chip enable.  Memory is then
addressed with the CE, PSEN and RD enable pins.

>From what I've read the ROM_INIT portion of the bootloader sets up the
following as the "default" in the 400:
1) All of the chip enable pins are used as chip enables and not GPIO
2) Each chip enable is capable of addressing 2 MB of memory
3) The peripheral chip enables pins are used as peripheral chip enables
and not GPIO
4) Each peripheral chip enable is capable of addressing 1 MB of memory
5) The program and data memory spaces are combined

What I believe this does is that even though the peripheral chip enables
are active and can address 1 MB each, they are never asserted when the
400 chip does memory operations since the memory map does not point to
data memory anymore.  Instead it points to combined program and data
memory which is enabled through the chip enables.

Therefore, when I use the dataport class or I do MOVC or MOVX
instructions the chip enables are asserted with PSEN and RD depending on
whether I'm reading or writing.

Hopefully this has all been correct so far since I've been pouring over
these documents all week.

What I'm less sure about is how to reverse the default settings and open
up the peripheral chip enables.

I think I need to do create a native method to do the following:
1) Disable interrupts
2) Push MCON1, MCON, P4CNT, P5CNT, P6CNT onto the stack
3) Use the timed-access procedure (MOV 0c7h, #0AAh and MOV 0C7h, #55h)
to access protecting registers (MCON, MCON1)
4) Split the program and data memory apart by editing MCON1.3-0 and/or
MCON.3-0
5) Timed-access procedure to access P5CNT
6) Enable needed PCE signals
7) UNSURE: Timed-access procedure to access P6CNT and P4CNT
8) UNSURE: disable CE signals that would overlap PCE space
9) Perform memory operations
10) Pop MCON1, MCON, P4CNT, P5CNT, P6CNT from the stack
11) Enable interrupts

Is the above correct?
Do I need to disable CE's?  (I don't need them as GPIO in the routine)
Is there a method to enable/disable interrupts or do I just modify a
register?
Do I need to set CE to 2MB and PCE to 1MB or can I just assume the
registers are the same as the default?

How do I perform a memory operation into my PCE space?  If my PCE's are
set to 1MB each, then PCE3 runs from 0x200000 to 0x2FFFFF.  Correct?
Since I need to set A0-A2 in order to select the 7 registers in the DSP
does this mean that my memory space looks like 0x2XXXXA with A equal to
the address of the register I want?

How do I get to this space?  In the 390 the PCE space was mapped
0x800000 above the CE space.  How is this done in the 400?  Do I need to
disable the corresponding CE space and then the 400 chip will just do
the addressing for me?  I don't know much about assembly language, are
there different memory instructions for program and data memory (Maybe
the MOVC and MOVX I've read about?).

Also, Don's book says that PCE memory accesses are a lot slower than CE
memory accesses.  Is this so?  If so, why?  Should we be programming the
DSP using CE's instead of PCE's?

Thanks a lot,
Jonathan Sharret

TELEGRID Technologies, Inc.
Email: j.sharret-vt2K7lilQm9Wk0Htik3J/[email protected]


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