Re: Parallel I/O

Jonathan Sharret wrote:
> What I believe this does is that even though the peripheral chip enables
> are active and can address 1 MB each, they are never asserted when the
> 400 chip does memory operations since the memory map does not point to
> data memory anymore.  Instead it points to combined program and data
> memory which is enabled through the chip enables.
> 
> Therefore, when I use the dataport class or I do MOVC or MOVX
> instructions the chip enables are asserted with PSEN and RD depending on
> whether I'm reading or writing.

Correct.

> What I'm less sure about is how to reverse the default settings and open
> up the peripheral chip enables.
> 
> I think I need to do create a native method to do the following:
> 1) Disable interrupts
> 2) Push MCON1, MCON, P4CNT, P5CNT, P6CNT onto the stack
> 3) Use the timed-access procedure (MOV 0c7h, #0AAh and MOV 0C7h, #55h)
> to access protecting registers (MCON, MCON1)
> 4) Split the program and data memory apart by editing MCON1.3-0 and/or
> MCON.3-0
> 5) Timed-access procedure to access P5CNT
> 6) Enable needed PCE signals
> 7) UNSURE: Timed-access procedure to access P6CNT and P4CNT

Most likely not required.

> 8) UNSURE: disable CE signals that would overlap PCE space

When PCE and CE are both enabled, code fetches will go to CE and data 
fetches will go to PCE.  Also, all PCE reads are with /RD and all CE 
reads are with /PCE.

> 9) Perform memory operations
> 10) Pop MCON1, MCON, P4CNT, P5CNT, P6CNT from the stack
> 11) Enable interrupts

> Is the above correct?
> Do I need to disable CE's?  (I don't need them as GPIO in the routine)
> Is there a method to enable/disable interrupts or do I just modify a
> register?

No.

> Do I need to set CE to 2MB and PCE to 1MB or can I just assume the
> registers are the same as the default?

You can leave these default.

> How do I perform a memory operation into my PCE space?  If my PCE's are
> set to 1MB each, then PCE3 runs from 0x200000 to 0x2FFFFF.  Correct?
> Since I need to set A0-A2 in order to select the 7 registers in the DSP
> does this mean that my memory space looks like 0x2XXXXA with A equal to
> the address of the register I want?

Yes.

> How do I get to this space?  In the 390 the PCE space was mapped
> 0x800000 above the CE space.  How is this done in the 400?  Do I need to
> disable the corresponding CE space and then the 400 chip will just do
> the addressing for me?  I don't know much about assembly language, are
> there different memory instructions for program and data memory (Maybe
> the MOVC and MOVX I've read about?).

TINIOS does not have the capability to access PCE space on the 400 as 
all 16Mbytes of address space are allocated to /CE.

> Also, Don's book says that PCE memory accesses are a lot slower than CE
> memory accesses.  Is this so?  If so, why?  Should we be programming the
> DSP using CE's instead of PCE's?

Because on the '390, switching between CE and PCE to copy adds time to 
the copy operation.


-Bryan

-- 
--
Bryan Armstrong
bryan.armstrong-6tN4nzCoH/[email protected]


_______________________________________________
TINI mailing list
TINI-6tN4nzCoH/[email protected]
To UNSUBSCRIBE, edit your profile, or see list archives:
http://lists.dalsemi.com/mailman/listinfo/tini