SPI Bus Speed depending on CPU frequency of the DS80C400 TINI OS 1.12?

Hello list,

According to the documentation of the SPI Class ->

    This class is a thin wrapper over a bit-bang SPI native library.
    The bit-bang SPI port is implemented using pins ... (PCE0\-PCE3\) of
    the DS80C390. This is a master only implementation. P5.4 (PCE0\) =
    SSCK (Serial clock) P5.5 (PCE1\) = MOSI (Master Out/Slave In) P5.6
    (PCE2\) = MISO (Master In/Slave Out) P5.7 (PCE3\) = SS (Slave select)

        * Max data rate is 100Kbit/s. Lower frequencies are specified
          using a clock delay value that can be set using the
          setClockDelay method.

    Note on noskew option: Do not attempt to use the noskew option of
    this SPI library with a *Large* Data Array. Using noskew turns off
    interrupts on TINI and will cause UNPREDICTABLE system behavior and
    watch dog reboots sending of a *Large* data array is attempted.

the MAX DATA Rate is about 100Kbit. Why is this set to this small value 
(according to SPI specification the max value allowed is 1 Mbit!), and 
how does this value depend on the CPU frequency? Is it compared to a 
TINI m400 Board with 29.xx MHz and do I have the 2.5 times faster access 
with a 73.728 Mhz Board??

And: Does this Max value belong to the fact, that TIMER3 and TIMER1 are 
used for serial port timings and so there is no way to clock it correctly?
Has anybody made experiences with higher speeds on the SPI Bus and could 
share this experience?

kind regards
Peter

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