RE: SPI Bus Speed depending on CPU frequency of the DS80C400 TINI OS 1.12?
"Jeremy Kongs" <jeremy.kongs-6tN4nzCoH/[email protected]> Thu, 20 May 2004 08:09:19 -0500
| Newsgroups | gmane.comp.hardware.microcontrollers.tini |
|---|---|
| Message-ID | <[email protected]> |
Since TINI uses a software SPI library it is only capable of 100Kbits/s. It takes much longer to control the signals directly by software than just getting and putting bytes into a register for a hardware SPI solution. Faster clock speeds will yield higher throughput. Some on this list have implemented a hardware SPI solution in the CPLD (U12). > -----Original Message----- > From: tini-admin-6tN4nzCoH/[email protected] [mailto:tini-admin-6tN4nzCoH/[email protected]]On Behalf Of > Peter in Afrika > Sent: Wednesday, May 19, 2004 7:39 AM > To: tini-6tN4nzCoH/[email protected] > Subject: [TINI]SPI Bus Speed depending on CPU frequency of the DS80C400 > TINI OS 1.12? > > > Hello list, > > According to the documentation of the SPI Class -> > > This class is a thin wrapper over a bit-bang SPI native library. > The bit-bang SPI port is implemented using pins ... (PCE0\-PCE3\) of > the DS80C390. This is a master only implementation. P5.4 (PCE0\) = > SSCK (Serial clock) P5.5 (PCE1\) = MOSI (Master Out/Slave In) P5.6 > (PCE2\) = MISO (Master In/Slave Out) P5.7 (PCE3\) = SS (Slave select) > > * Max data rate is 100Kbit/s. Lower frequencies are specified > using a clock delay value that can be set using the > setClockDelay method. > > Note on noskew option: Do not attempt to use the noskew option of > this SPI library with a *Large* Data Array. Using noskew turns off > interrupts on TINI and will cause UNPREDICTABLE system behavior and > watch dog reboots sending of a *Large* data array is attempted. > > the MAX DATA Rate is about 100Kbit. Why is this set to this small value > (according to SPI specification the max value allowed is 1 Mbit!), and > how does this value depend on the CPU frequency? Is it compared to a > TINI m400 Board with 29.xx MHz and do I have the 2.5 times faster access > with a 73.728 Mhz Board?? > > And: Does this Max value belong to the fact, that TIMER3 and TIMER1 are > used for serial port timings and so there is no way to clock it correctly? > Has anybody made experiences with higher speeds on the SPI Bus and could > share this experience? > > kind regards > Peter > > _______________________________________________ > TINI mailing list > TINI-6tN4nzCoH/[email protected] > To UNSUBSCRIBE, edit your profile, or see list archives: > http://lists.dalsemi.com/mailman/listinfo/tini _______________________________________________ TINI mailing list TINI-6tN4nzCoH/[email protected] To UNSUBSCRIBE, edit your profile, or see list archives: http://lists.dalsemi.com/mailman/listinfo/tini